公开(公告)号：US20210091301A1

公开(公告)日：2021-03-25

申请号：US16578729

申请日：2019-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John Arnold ,  Dominik Metzler ,  Ashim Dutta ,  Donald Canaperi

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10 ,  H01L43/12

Abstract: Methods for forming an integrated circuit are provided. Aspects include providing a wafer substrate having an embedded memory area interconnect structure and an embedded non-memory area interconnect structure, the memory area interconnect structure comprising metal interconnects formed within a first interlayer dielectric, recessing a portion of the memory area interconnect structure, forming a bottom electrode contact on the recessed portion of the memory area interconnect structure, forming a bottom electrode over the bottom electrode contact, forming a protective dielectric layer over the non-memory area interconnect structure, and forming memory element stack layers on a portion of the bottom electrode.

公开(公告)号：US20210090951A1

公开(公告)日：2021-03-25

申请号：US16580567

申请日：2019-09-24

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John C. Arnold ,  Ashim Dutta ,  Dominik Metzler ,  Ekmini A. De Silva

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/522

Abstract: A method for fabricating a semiconductor device includes recessing a first odd hardmask and a first even hardmask to form recessed odd and even hardmasks, forming a first conductive hardmask including first conductive hardmask material on the recessed odd hardmask and a second conductive hardmask on the recessed even hardmask, and forming self-aligned vias at line ends corresponding to the first odd and even conductive lines based at least in part on the first and second conductive hardmasks.

公开(公告)号：US20210082746A1

公开(公告)日：2021-03-18

申请号：US16570059

申请日：2019-09-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John C. Arnold ,  Ashim Dutta ,  Dominik Metzler ,  Timothy M. Philip ,  Sagarika Mukesh

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/522

Abstract: Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.

公开(公告)号：US20210013400A1

公开(公告)日：2021-01-14

申请号：US16506459

申请日：2019-07-09

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Saba Zare ,  Michael Rizzolo ,  Theodorus E. Standaert ,  Daniel Charles Edelstein

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  G11C11/16

Abstract: A method of forming a semiconductor structure includes forming a dielectric layer surrounding contacts over a top surface and bevel edge of a substrate, forming a sacrificial buffer layer over the dielectric layer, removing portions of the sacrificial buffer layer formed over the dielectric layer on the top surface of the substrate, and patterning device structures including one or more metal layers over the contacts, wherein patterning the device structures removes portions of the metal layers formed over the top surface of the substrate leaving the metal layers on the bevel edge. The method also includes forming an encapsulation layer and performing a bevel dry etch to remove the encapsulation layer and the metal layers on the bevel edge. The bevel dry etch damages the sacrificial buffer layer on the bevel edge underneath the metal layers. The method further includes removing the damaged sacrificial buffer layer from the bevel edge.

公开(公告)号：US20200350177A1

公开(公告)日：2020-11-05

申请号：US16400003

申请日：2019-04-30

Applicant: International Business Machines Corporation

Inventor： Nelson Felix ,  Ekmini Anuja De Silva ,  Praveen Joseph ,  Ashim Dutta

IPC: H01L21/308 ,  H01L21/033

Abstract: An initial semiconductor structure includes an underlying substrate, a hard mask stack, an organic planarization layer (OPL), a first complementary material, and a patterned photoresist layer patterned into a plurality of photoresist pillars defining a plurality of photoresist trenches. The first material is partially etched inward of the trenches, to provide trench regions, and the photoresist is removed. The trench regions are filled with a second complementary material, preferentially etchable with respect to the first material. A polymer brush is grafted on the second material but not the first material, to form polymer brush regions with intermediate regions not covered by the brush. The first material is anisotropically etched the at the intermediate regions but not the brush regions. The OPL is etched inward of the intermediate regions, to provide a plurality of OPL pillars defining a plurality of OPL trenches inverted with respect to the photoresist pillars.

公开(公告)号：US10707413B1

公开(公告)日：2020-07-07

申请号：US16368209

申请日：2019-03-28

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  John C. Arnold ,  Michael Rizzolo ,  Jon Slaughter

IPC: H01L43/12 ,  G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L27/12

Abstract: Techniques are provided for fabricating magnetic random-access memory devices, which eliminate junction shorts and minimize gouging of an underlying insulating layer. For example, a bottom electrode layer, a magnetic tunnel junction (MTJ) stack, and an upper electrode layer are formed over an insulating layer. The bottom electrode layer and the MTJ stack are etched to form an upper electrode and a MTJ structure. A cleaning etch process removes residual metallic material which is re-deposited on sidewalls of the MTJ structure as a result of etching the MTJ stack. A conformal dielectric layer is formed to encapsulate the upper electrode and the MTJ structure and prevent oxidation or re-deposition of metallic material on the cleaned sidewalls of the MTJ structure. A final etch process is performed to pattern the conformal dielectric layer and bottom electrode layer to form a spacer on sidewalls of the MTJ structure and form a bottom electrode.

公开(公告)号：US10672618B2

公开(公告)日：2020-06-02

申请号：US16032759

申请日：2018-07-11

Applicant: Tokyo Electron Limited ,  International Business Machines Corporation

Inventor： Vinh Luong ,  Isabel Cristina Chu ,  Ashim Dutta

IPC: H01L21/3065 ,  H01L21/033 ,  H01L21/311 ,  H01L21/3213 ,  H01J37/32

Abstract: Embodiments of systems and methods for patterning features in tantalum nitride (TaN) are described. In an embodiment, a method may include receiving a substrate comprising a TaN layer. The method may also include etching the substrate to expose at least a portion of the TaN layer. Additionally, the method may include performing a passivation process to reduce lateral etching of the TaN layer. The method may further include etching the TaN layer to form a feature therein, wherein the passivation process is controlled to meet one or more target passivation objectives.

公开(公告)号：US20250107113A1

公开(公告)日：2025-03-27

申请号：US18474647

申请日：2023-09-26

Applicant: International Business Machines Corporation

Inventor： Ashim Dutta ,  Brandon Noland Canedy ,  Chih-Chao Yang

IPC: H01C1/14 ,  H01C17/06 ,  H01L23/522

Abstract: Aspects of the present invention provide a three-dimensional resistor with at least two horizontal resistive metal elements connected by at least one vertical resistive metal element. Each of the vertical resistive metal elements surrounds a portion of a first dielectric material where the portion of resistive metal surrounding the dielectric material forms a tube of the resistive metal. More than one vertical resistive metal element with a thickness between one and five nanometers can be present between each of two adjacent horizontal resistive metal elements.

公开(公告)号：US20250096124A1

公开(公告)日：2025-03-20

申请号：US18469649

申请日：2023-09-19

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ashim Dutta ,  Chih-Chao Yang ,  Shravana Kumar Katakam

IPC: H01L23/525

Abstract: An antifuse structure including a first fuse conductor, a second fuse conductor in the same metallization level as the second fuse conductor, and a tapered fuse dielectric between and separating the first fuse conductor from the second fuse conductor.

公开(公告)号：US12243771B2

公开(公告)日：2025-03-04

申请号：US17666767

申请日：2022-02-08

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John C. Arnold ,  Ashim Dutta ,  Dominik Metzler ,  Timothy M. Philip ,  Sagarika Mukesh

IPC: H01L21/768 ,  H01L21/033 ,  H01L23/522

Abstract: Methods and structures for forming vias are provided. The method includes forming a structure that includes an odd line hardmask and an even line hardmask. The odd line hardmask and the even line hardmask include different hardmask materials that have different etch selectivity with respect to each other. The method includes patterning vias separately into the odd line hardmask and the even line hardmask based on the different etch selectivity of the different hardmask materials. The method also includes forming via plugs at the vias. The method includes cutting even line cuts and odd line cuts into the structure. The even line cuts and the odd line cuts are self-aligned with the vias. The vias are formed at line ends of the structure.