公开(公告)号：US20250101357A1

公开(公告)日：2025-03-27

申请号：US18472703

申请日：2023-09-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： John S. Werner ,  Steven Holmes ,  Benjamin Hardy Wunsch ,  Sagarika Mukesh ,  Arkadiy O. Tsfasman

IPC: C12M1/12 ,  C12N5/0793 ,  G06T7/00 ,  G06V10/82 ,  G06V20/69

Abstract: A method, system, and computer program product are provided for monitoring neuron growth within a lattice and stopping a spread of an infection. An infection visual recognition module monitors and captures images of the lattice during the neuron growth. The presence of the infection in the neurons within the lattice is identified. The identifying includes performing, via a deep neural network, visual recognition on the captured images to identify the presence of the infection. In response to the identifying, applying a laser to the infected area of the lattice with sufficient energy for stopping the infection. The lattice is flushed to remove chemical byproducts and dead cells resulting from the laser application.

公开(公告)号：US12148699B2

公开(公告)日：2024-11-19

申请号：US17806570

申请日：2022-06-13

Applicant: International Business Machines Corporation

Inventor： Sagarika Mukesh ,  Devika Sarkar Grant ,  Fee Li Lie ,  Hosadurga Shobha ,  Thamarai selvi Devarajan ,  Aakrati Jain

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/532

Abstract: A semiconductor component includes an area of dielectric material extending below an uppermost surface of a substrate. The semiconductor component further includes a trench formed so as to extend from above the uppermost surface of the substrate into the area of dielectric material. The semiconductor component further includes a non-metal liner coating interior surfaces of the trench. The semiconductor component further includes a metal liner coating interior surfaces of the non-metal liner. The semiconductor component further includes a power rail formed in the trench in direct contact with at least one of the metal liner or the non-metal liner such that the power rail extends into the area of dielectric material and above the uppermost surface of the substrate.

公开(公告)号：US20240347423A1

公开(公告)日：2024-10-17

申请号：US18298402

申请日：2023-04-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Sagarika Mukesh ,  Shravana Kumar Katakam ,  Tao Li ,  Ruilong Xie ,  Nicholas Anthony Lanzillo ,  Julien Frougier

IPC: H01L23/48 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/823412 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/775 ,  H01L29/78696

Abstract: Embodiments of present invention provide a semiconductor structure. The structure includes an array of transistors on a semiconductor substrate, the array of transistors including a first transistor and a second transistor, the second transistor being next to the first transistor; and a metal connection between the first transistor and the second transistor, wherein the metal connection connects a first metal contact at a frontside of the array of transistors to a second metal contact at a backside of the array of transistors. A method of forming the same is also provided.

公开(公告)号：US12080709B2

公开(公告)日：2024-09-03

申请号：US17655595

申请日：2022-03-21

Applicant: International Business Machines Corporation

Inventor： Sagarika Mukesh ,  Julien Frougier ,  Nicolas Jean Loubet ,  Ruilong Xie

IPC: H01L27/06 ,  H01L21/822 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L27/1222 ,  H01L27/1251 ,  H01L27/127 ,  H01L29/78696

Abstract: A semiconductor device includes a bottom device, a top device, and a spacer. The bottom device includes a first set of silicon sheets and a first source-drain epitaxy in direct contact with the first set of silicon sheets. The top device includes a second set of silicon sheets, a set of separation layers, and a second source-drain epitaxy. Each silicon sheet of the second set of silicon sheets is separated by a separation layer of the set of separation layers. The second source-drain epitaxy is arranged in direct contact with the second set of silicon sheets. The spacer is arranged between the first source-drain epitaxy and the second source-drain epitaxy and is arranged between each silicon sheet of the second set of silicon sheets.

公开(公告)号：US20240203904A1

公开(公告)日：2024-06-20

申请号：US18083994

申请日：2022-12-19

Applicant: International Business Machines Corporation

Inventor： FEE LI LIE ,  Hosadurga Shobha ,  Michael Rizzolo ,  Aakrati Jain ,  Sagarika Mukesh ,  Christopher J. Waskiewicz

IPC: H01L23/00

CPC classification number: H01L23/562 ,  H01L23/5226

Abstract: A semiconductor structure is provided that includes a stress modulating pattern containing bonding dielectric layer. The stress modulating pattern containing bonding dielectric layer can be formed on a wafer, on a device-containing region that is present on a device wafer, or both a wafer and a device-containing region that is present on a device wafer. The stress modulating pattern is composed of a plurality of patterned structures (metal and/or dielectric) that are embedded at least partially within a bonding dielectric layer. Warpage modulation can be achieved using such a stress modulating pattern containing bonding dielectric layer.

公开(公告)号：US20230369218A1

公开(公告)日：2023-11-16

申请号：US17662859

申请日：2022-05-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Tao Li ,  Devika Sarkar Grant ,  Liqiao Qin ,  Nikhil Jain ,  Prabudhya Roy Chowdhury ,  Sagarika Mukesh ,  Ruilong Xie ,  Kisik Choi

IPC: H01L23/528 ,  H01L21/8234 ,  H01L21/768 ,  H01L23/522 ,  H01L29/786

CPC classification number: H01L23/5286 ,  H01L21/823475 ,  H01L21/76897 ,  H01L23/5226 ,  H01L29/78696 ,  H01L29/0673

Abstract: Embodiments disclosed herein include a semiconductor structure. The semiconductor structure may include a first top transistor comprising a first source/drain (S/D) region and a first bottom transistor with a second S/D region. The first bottom transistor may be stacked directly below the first transistor. The semiconductor structure may also include a backside power delivery network (BSPDN) below the bottom transistor, a back-end-of-line (BEOL) metal level above the top transistor, and a first interlevel via electrically connecting a top of the first S/D region to the BSPDN.

公开(公告)号：US11094590B1

公开(公告)日：2021-08-17

申请号：US16813682

申请日：2020-03-09

Applicant: International Business Machines Corporation

Inventor： Sagarika Mukesh ,  Dominik Metzler ,  Chanro Park ,  Timothy Mathew Philip

IPC: H01L21/768 ,  H01L23/522 ,  H01L21/3213

Abstract: Techniques for forming self-aligned subtractive top vias using a via hardmask supported by scaffolding are provided. In one aspect, a method of forming top vias includes: forming metal lines on a substrate using line hardmasks; patterning vias in the line hardmasks; filling the vias and trenches in between the metal lines with a via hardmask material to form via hardmasks and a scaffolding adjacent to and supporting the via hardmasks; removing the line hardmasks; and recessing the metal lines using the via hardmasks to form the top vias that are self-aligned with the metal lines. The scaffolding can also be placed prior to patterning of the vias in the line hardmasks. A structure formed in accordance with the present techniques containing top vias is also provided.

公开(公告)号：US20250098245A1

公开(公告)日：2025-03-20

申请号：US18470669

申请日：2023-09-20

Applicant: International Business Machines Corporation

Inventor： Sagarika Mukesh ,  Alexander Reznicek ,  Tao Li ,  Ruilong Xie

IPC: H01L29/08 ,  H01L21/02 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775

Abstract: A semiconductor device comprises a stacked structure, the stacked structure comprising a plurality of gate structures alternately stacked with a plurality of channel layers. At least one epitaxial source/drain region disposed on a side of the stacked structure, and the stacked structure is disposed on at least one dielectric layer. A portion of the at least one epitaxial source/drain region is disposed in the at least one dielectric layer.

公开(公告)号：US20240429283A1

公开(公告)日：2024-12-26

申请号：US18337787

申请日：2023-06-20

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Sagarika Mukesh ,  Tsung-Sheng Kang ,  Ruilong Xie

IPC: H01L29/08 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a field effect transistor (FET). The FET includes a source/drain (S/D) epitaxy and a metal gate. Additionally, the semiconductor structure includes a backside epitaxy in electrical contact with the S/D epitaxy. Further, the backside epitaxy includes a highly doped epitaxy. Additionally, the semiconductor structure includes a backside contact in electrical contact with the backside epitaxy. Further, the semiconductor structure includes a backside power distribution network in electrical contact with the backside contact.

公开(公告)号：US20240332294A1

公开(公告)日：2024-10-03

申请号：US18192247

申请日：2023-03-29

Applicant: International Business Machines Corporation

Inventor： Ruilong Xie ,  Tsung-Sheng Kang ,  Alexander Reznicek ,  Sagarika Mukesh

IPC: H01L27/092 ,  H01L21/8234 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L27/092 ,  H01L21/823481 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/775

Abstract: Embodiments are disclosed for a semiconductor structure. The semiconductor structure includes a first pair of field effect transistors (FETs). Additionally, the semiconductor structure includes a second pair of FETs. Further, the semiconductor structure includes a shallow gate cut that separates a first pair of gates, a first pair of channels, and a first pair of source/drain (S/D) epitaxies of the first pair of FETs. Additionally, the first pair of S/D epitaxies are wired to a backside power rail (BPR) by a backside contact. Further, the semiconductor structure includes a deep gate cut that separates a second pair of S/D epitaxies of the second pair of FETs. Additionally, one of the second pair of S/D epitaxies is wired to a back end of line (BEOL) interconnect via a frontside contact. Further, another of the second pair of S/D epitaxies is wired to the BPR by a backside contact.