公开(公告)号：US20210151565A1

公开(公告)日：2021-05-20

申请号：US17134868

申请日：2020-12-28

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Ruilong Xie ,  Chi-Chun Liu ,  Cheng Chi ,  Kangguo Cheng

IPC: H01L29/10 ,  H01L21/02 ,  H01L29/16 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L21/308

Abstract: Semiconductor devices include channel structures, arranged in vertically aligned pairs of channel structures. A gate stack is formed around all of the plurality of channel structures, filling a space between each pair of channel structures. Inner spacers are formed at respective ends of the channel structures, each having a vertical central portion and horizontal portions that extend outward from sides of the central portion, between the channels.

公开(公告)号：US10832943B2

公开(公告)日：2020-11-10

申请号：US16372716

申请日：2019-04-02

Applicant: International Business Machines Corporation

Inventor： Su Chen Fan ,  Cheng Chi ,  Kangguo Cheng ,  Ruilong Xie

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/522

Abstract: A method for forming a semiconductor structure is provided. The method includes depositing a dielectric material in a first opening above a first source/drain region in a first region of the semiconductor structure and in a second and a third opening above a respective second and a third source/drain region in a second region of the silicon structure. There is a gate region between the second and third source/drain regions. The method etches away the dielectric material deposited in the first opening and deposits an organic material in the first opening. The method further etches a region above the gate region between the second and third source/drain regions to expose the gate region and form a fourth opening and removes the organic material from the first opening. The method deposits a metal in the first opening and the fourth opening.

公开(公告)号：US20200321244A1

公开(公告)日：2020-10-08

申请号：US16372716

申请日：2019-04-02

Applicant: International Business Machines Corporation

Inventor： Su Chen Fan ,  Cheng Chi ,  Kangguo Cheng ,  Ruilong Xie

IPC: H01L21/768 ,  H01L23/522 ,  H01L29/78

Abstract: A method for forming a semiconductor structure is provided. The method includes depositing a dielectric material in a first opening above a first source/drain region in a first region of the semiconductor structure and in a second and a third opening above a respective second and a third source/drain region in a second region of the silicon structure. There is a gate region between the second and third source/drain regions. The method etches away the dielectric material deposited in the first opening and deposits an organic material in the first opening. The method further etches a region above the gate region between the second and third source/drain regions to expose the gate region and form a fourth opening and removes the organic material from the first opening. The method deposits a metal in the first opening and the fourth opening.

公开(公告)号：US10763342B2

公开(公告)日：2020-09-01

申请号：US16216356

申请日：2018-12-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Cheng Chi ,  Ruilong Xie

IPC: H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L21/8238 ,  H01L21/285 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/8234

Abstract: A method is presented for forming equal thickness gate spacers for a CMOS (complementary metal oxide semiconductor) device, the method includes forming a PFET (p-type field effect transistor) device and an NFET (n-type field effect transistor) device each including gate masks formed over dummy gates, forming PFET epi growth regions between the dummy gates of the PFET device, forming NFET epi growth regions between the dummy gates of the NFET device, depositing a nitride liner and an oxide over the PFET and NFET epi growth regions, the nitride liner and oxide extending up to the gate masks, and removing the dummy gates and the gate masks to form HKMGs (high-k metal gates) between the PFET and NFET epi growth regions.

公开(公告)号：US20200006476A1

公开(公告)日：2020-01-02

申请号：US16545867

申请日：2019-08-20

Applicant: International Business Machines Corporation

Inventor： Robin Hsin Kuo Chao ,  Kangguo Cheng ,  Cheng Chi ,  Ruilong Xie ,  John H. Zhang

IPC: H01L29/06 ,  H01L29/775 ,  H01L29/66

Abstract: A substrate structure for a nanosheet transistor includes a plurality of nanosheet layers and a plurality of recesses between the nanosheet layers. The substrate structure includes at least one trench through portions of the nanosheet layers, the sacrificial layers, and the substrate. The substrate structure includes a u-shaped portion formed at a bottom portion of the at least one trench. The u-shaped portion includes a bottom cavity. The substrate structure further includes a first liner disposed upon the u-shaped portion of the at least one trench, and a second liner disposed on the first liner. The substrate structure further includes a third liner disposed within the at least one trench to fill the bottom cavity of the u-shaped portion to form a bottom inner spacer within the bottom cavity.

公开(公告)号：US20190341489A1

公开(公告)日：2019-11-07

申请号：US16507683

申请日：2019-07-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng Chi ,  Tenko Yamashita ,  Chen Zhang

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/08 ,  H01L27/12 ,  H01L29/786

Abstract: A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a recessed region in a substrate and a fin region adjacent to the recessed region, forming one or more vertical fins on the fin region, forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins, forming two or more long-channel source/drain plugs on the long-channel pillar, forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins, forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins, and forming a top source/drain on the top surface of the one or more vertical fins.

公开(公告)号：US20190334033A1

公开(公告)日：2019-10-31

申请号：US16507843

申请日：2019-07-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng Chi ,  Tenko Yamashita ,  Chen Zhang

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/08 ,  H01L27/12 ,  H01L29/786

Abstract: A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a recessed region in a substrate and a fin region adjacent to the recessed region, forming one or more vertical fins on the fin region, forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins, forming two or more long-channel source/drain plugs on the long-channel pillar, forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins, forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins, and forming a top source/drain on the top surface of the one or more vertical fins.

公开(公告)号：US10461174B1

公开(公告)日：2019-10-29

申请号：US16020061

申请日：2018-06-27

Applicant: International Business Machines Corporation

Inventor： Cheng Chi ,  Hao Tang ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L21/8238 ,  H01L23/532

Abstract: A method of forming a semiconductor device includes: forming a bottom source or drain (S/D) layer on a substrate; forming a bottom spacer layer on the bottom S/D layer; forming a vertical transistor channel on the bottom S/D; forming a high-k metal gate layer on sides of the vertical transistor channel and above the bottom S/D layer; forming a gate spacer on sides of the vertical transistor channel and on top of the high-k metal gate layer; covering the high-k metal gate layer, the vertical transistor channel and bottom S/D layer with an interlayer dielectric (ILD); forming with a non-self-aligned contact (SAC) etch a bottom S/D recess through the ILD to expose the bottom S/D layer, the etch removing at least portion of the gate spacer and the high-k metal gate layer; and forming a bottom S/D contact spacer on sides of the bottom S/D recess.

公开(公告)号：US10411127B2

公开(公告)日：2019-09-10

申请号：US16046123

申请日：2018-07-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Cheng Chi ,  Tenko Yamashita ,  Chen Zhang

IPC: H01L21/8234 ,  H01L29/78 ,  H01L27/088 ,  H01L29/08 ,  H01L29/423 ,  H01L29/66

Abstract: A method of forming a vertical transport fin field effect transistor and a long-channel field effect transistor on the same substrate, including, forming a recessed region in a substrate and a fin region adjacent to the recessed region, forming one or more vertical fins on the fin region, forming a long-channel pillar from the substrate in the recessed region, where the long-channel pillar is at a different elevation than the one or more vertical fins, forming two or more long-channel source/drain plugs on the long-channel pillar, forming a bottom source/drain plug in the fin region, where the bottom source/drain plug is below the one or more vertical fins, forming a gate structure on the long-channel pillar and a gate structure on the one or more vertical fins, and forming a top source/drain on the top surface of the one or more vertical fins.

公开(公告)号：US10263099B2

公开(公告)日：2019-04-16

申请号：US15876606

申请日：2018-01-22

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc.

Inventor： Cheng Chi ,  Fee Li Lie ,  Chi-Chun Liu ,  Ruilong Xie

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L21/033 ,  H01L21/3105 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161 ,  H01L29/22 ,  H01L29/49 ,  H01L29/51

Abstract: A method for fabricating a semiconductor device comprises forming a first hardmask, a planarizing layer, and a second hardmask on a substrate. Removing portions of the second hardmask and forming alternating blocks of a first material and a second material over the second hardmask. The blocks of the second material are removed to expose portions of the planarizing layer. Exposed portions of the planarizing layer and the first hardmask are removed to expose portions of the first hardmask. Portions of the first hardmask and portions of the substrate are removed to form a first fin and a second fin. Portions of the substrate are removed to further increase the height of the first fin and substantially remove the second fin. A gate stack is formed over a channel region of the first fin.