公开(公告)号：US20180357558A1

公开(公告)日：2018-12-13

申请号：US15617860

申请日：2017-06-08

Applicant: International Business Machines Corporation

Inventor： Jing Ding ,  Jing Li ,  Ji Jiang Song ,  Jian Wang

IPC: G06N99/00 ,  G06F17/30 ,  G06N5/04

CPC classification number: G06N99/005 ,  G06F17/30312 ,  G06F17/30371 ,  G06N5/047

Abstract: The subject disclosure relates to employing grouping and selection components to facilitate a grouping of failure data associated with oil and gas exploration equipment into one or more equipment failure type groups. In an example, a method comprises grouping, by a system operatively coupled to a processor, training data of a set of equipment failure data into one or more failure type groups based on one or more determined failure criteria, wherein the one or more failure type groups represent equipment failure classifications associated with energy exploration processes; and selecting, by the system, first ungrouped data from the set of equipment failure data based on a level of similarity between the first ungrouped data and the training data.

公开(公告)号：US20180227358A1

公开(公告)日：2018-08-09

申请号：US15956122

申请日：2018-04-18

Applicant: International Business Machines Corporation

Inventor： Feng Gao ,  Peng Hui Jiang ,  Jing Li ,  Qin Li ,  Guang H. Sui ,  Bin Xu ,  Jian Hua Zhang

IPC: H04L29/08 ,  H04L29/06

CPC classification number: H04L67/06 ,  H04L67/10 ,  H04L67/2842 ,  H04L67/42

Abstract: A method for distributed file transfers with high performance and reliability includes creating, on a first Trivial File Transfer Protocol (TFTP) server, a global cache, where the global cache is used to store up to a first portion of a data file. The method further includes storing, on the first TFTP server, in the global cache, one or more continuous data blocks that have exceeded a defined first request rate threshold, where the one or more continuous data blocks make up a subset of the data blocks of the first portion of the data file. The method further includes predicting, on the first TFTP server, a next data block in the data file to be stored in the global cache and in response to predicting the next data block, storing, on the first TFTP server, the next data block in the global cache.

公开(公告)号：US20180227356A1

公开(公告)日：2018-08-09

申请号：US15794302

申请日：2017-10-26

Applicant: International Business Machines Corporation

Inventor： Feng Gao ,  Peng Hui Jiang ,  Jing Li ,  Qin Li ,  Guang H. Sui ,  Bin Xu ,  Jian Hua Zhang

IPC: H04L29/08 ,  H04L29/06

Abstract: A method for distributed file transfers with high performance and reliability includes creating, on a first Trivial File Transfer Protocol (TFTP) server, a global cache, where the global cache is used to store up to a first portion of a data file. The method further includes storing, on the first TFTP server, in the global cache, one or more continuous data blocks that have exceeded a defined first request rate threshold, where the one or more continuous data blocks make up a subset of the data blocks of the first portion of the data file. The method further includes predicting, on the first TFTP server, a next data block in the data file to be stored in the global cache and in response to predicting the next data block, storing, on the first TFTP server, the next data block in the global cache.

公开(公告)号：US20150294232A1

公开(公告)日：2015-10-15

申请号：US14748850

申请日：2015-06-24

Applicant: International Business Machines Corporation

Inventor： Jing Li ,  Xiang Li ,  Haifeng Liu ,  Guo Tong Xie ,  Yi Qin Yu ,  Shi Lei Zhang

IPC: G06N7/00

Abstract: A method for detecting deviations between an event log and a process model includes converting the process model into a probability process model, the probability process model comprising multiple nodes in multiple hierarchies and probability distribution associated with the multiple nodes, a leaf node among the multiple nodes corresponding to an activity in the process model; detecting differences between at least one event sequence contained in the event log and the probability process model according to a correspondence relationship; and identifying the differences as the deviations in response to the differences exceeding a predefined threshold; wherein the correspondence relationship describes a correspondence relationship between an event in one event sequence of the at least one event sequence and a leaf node in the probability process model.

公开(公告)号：US09122404B2

公开(公告)日：2015-09-01

申请号：US13842375

申请日：2013-03-15

Applicant: International Business Machines Corporation

Inventor： Bing Dai ,  Chung H. Lam ,  Jing Li

IPC: G06F3/06

CPC classification number: G06F3/0616 ,  G06F3/0653 ,  G06F3/0688 ,  G11C16/28 ,  G11C16/349

Abstract: A wear leveling technique is employed in a memory device so that the cycling history of a memory block is represented by the cycling history of a representative memory cell or a small number of representative memory cells. A control logic block tracks the cycling history of the one or more representative memory cells. A table tabulating the predicted shift in an optimal value for a reference variable for a sensing circuit as a function of cycling history is provided within the memory device. Prior to sensing a memory cell, the control logic block checks the total number of cycling in the one or more representative memory cells and adjusts the value for the reference variable in the sensing circuit, thereby providing an optimal value for the reference variable in the sensing circuit for each sensing cycle of the memory device.

Abstract translation: 在存储器件中采用磨损均衡技术，使得存储器块的循环历史由代表性存储器单元或少量代表性存储器单元的循环历史来表示。 控制逻辑块跟踪一个或多个代表性存储器单元的循环历史。 在存储器件内提供了表示用于感测电路的参考变量的最佳值的预测偏移作为循环历史的函数的表格。 在感测存储器单元之前，控制逻辑块检查一个或多个代表性存储器单元中的循环总数，并调整感测电路中参考变量的值，从而为感测中的参考变量提供最佳值 电路用于存储器件的每个感测周期。

公开(公告)号：US08921820B2

公开(公告)日：2014-12-30

申请号：US13717701

申请日：2012-12-18

Applicant: International Business Machines Corporation

Inventor： Matthew J. BrightSky ,  Chung H. Lam ,  Jing Li ,  Alejandro G. Schrott ,  Norma E. Sosa Cortes

IPC: H01L29/00 ,  H01L47/00 ,  H01L29/04 ,  H01L29/06 ,  H01L47/02 ,  H01L45/00

CPC classification number: H01L45/1253 ,  H01L45/06 ,  H01L45/124 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

Abstract: A phase change memory cell and a method for fabricating the phase change memory cell. The phase change memory cell includes a bottom electrode and a first non-conductive layer. The first non-conductive layer defines a first well, a first electrically conductive liner lines the first well, and the first well is filled with a phase change material in the phase change memory cell.

Abstract translation: 相变存储单元及相变存储单元的制造方法。 相变存储单元包括底电极和第一非导电层。 第一非导电层限定第一阱，第一导电衬垫在第一阱中引导，并且第一阱在相变存储单元中填充有相变材料。

公开(公告)号：US20140256100A1

公开(公告)日：2014-09-11

申请号：US14036447

申请日：2013-09-25

Applicant: International Business Machines Corporation

Inventor： Chung H. Lam ,  Jing Li ,  Edward W. Kiewra

IPC: H01L29/66 ,  H01L27/105

CPC classification number: H01L29/66666 ,  G11C13/003 ,  G11C2213/79 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463

Abstract: A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to each source terminal of the memory cell access devices. The memory array also includes a first set of at least two vertical pillars positioned above and electrically coupled to the source line. A second set of vertical pillars electrically isolated from the source line and positioned such that the source line does not extend below the second set of vertical pillars is also included. Furthermore, gate terminals of the memory cell access devices laterally surround the first set of vertical pillars and the second set of vertical pillars. Finally, a first word line contact is positioned between two of the second set of vertical pillars. The first word line contact is electrically coupled to the gate terminals.

公开(公告)号：US20140252418A1

公开(公告)日：2014-09-11

申请号：US13786573

申请日：2013-03-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Chung H. Lam ,  Jing Li ,  Edward W. Kiewra

IPC: H01L21/8239 ,  H01L27/105

CPC classification number: H01L29/66666 ,  G11C13/003 ,  G11C2213/79 ,  H01L27/228 ,  H01L27/2454 ,  H01L27/2463

Abstract: A memory array and a method for electrically coupling memory cell access devices to a word line. The memory array includes a source line electrically coupled to each source terminal of the memory cell access devices. The memory array also includes a first set of at least two vertical pillars positioned above and electrically coupled to the source line. A second set of vertical pillars electrically isolated from the source line and positioned such that the source line does not extend below the second set of vertical pillars is also included. Furthermore, gate terminals of the memory cell access devices laterally surround the first set of vertical pillars and the second set of vertical pillars. Finally, a first word line contact is positioned between two of the second set of vertical pillars. The first word line contact is electrically coupled to the gate terminals.

Abstract translation: 一种用于将存储器单元访问设备电耦合到字线的存储器阵列和方法。 存储器阵列包括电耦合到存储器单元访问设备的每个源端的源极线。 存储器阵列还包括位于上方并电耦合到源极线的至少两个垂直柱的第一组。 第二组垂直柱与源极线电隔离并且定位成使得源极线不延伸到第二组垂直柱之下。 此外，存储器单元访问装置的栅极端子横向围绕第一组垂直支柱和第二组垂直支柱。 最后，第一个字线触点位于第二组垂直支柱之间。 第一字线触点电耦合到栅极端子。

公开(公告)号：US08658498B1

公开(公告)日：2014-02-25

申请号：US13969629

申请日：2013-08-19

Applicant: International Business Machines Corporation

Inventor： Chung H. Lam ,  Jing Li

IPC: H01L21/336

CPC classification number: H01L27/1052 ,  H01L21/823487 ,  H01L21/823885 ,  H01L29/0692 ,  H01L29/4236 ,  H01L29/4238 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66666 ,  H01L29/7827

Abstract: A method for fabricating vertical surround gate structures in semiconductor device arrays. The method includes forming pillars separated by vertical and horizontal trenches on a substrate. Forming a gate layer over the pillars and trenches such that the gate layer forms gate trenches in the horizontal trenches. The method includes forming fillers within the gate trenches, and planarizing the gate layer and fillers. The method also includes successively etching a first portion of the gate layer, removing the fillers, and etching a second portion of the gate layer.

Abstract translation: 一种在半导体器件阵列中制造垂直环绕栅极结构的方法。 该方法包括在衬底上形成由垂直和水平沟槽分隔的柱。 在柱和沟槽上形成栅极层，使得栅极层在水平沟槽中形成栅极沟槽。 该方法包括在栅极沟槽内形成填料，并平整栅极层和填料。 该方法还包括连续地蚀刻栅极层的第一部分，去除填料并蚀刻栅极层的第二部分。