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公开(公告)号：US11121209B2
公开(公告)日：2021-09-14
申请号：US15469860
申请日：2017-03-27
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Takashi Ando , Eduard A. Cartier , Hemanth Jagannathan , Paul C. Jamison , Vijay Narayanan
IPC: H01L49/02 , H01L23/522 , H01L21/02 , H01L21/285 , H01L23/48
Abstract: A method for forming a metal-insulator-metal (MIM) capacitor on a semiconductor substrate is presented. The method includes forming a first electrode defining columnar grains, forming a dielectric layer over the first electrode, and forming a second electrode over the dielectric layer. The first and second electrodes can be titanium nitride (TiN) electrodes. The dielectric layer can include one of hafnium oxide and zirconium oxide deposited by atomic layer deposition (ALD). The ALD results in deposition of high-k films in grain boundaries of the first electrode.
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公开(公告)号：US20200381624A1
公开(公告)日：2020-12-03
申请号：US16428554
申请日：2019-05-31
Inventor： Steven Consiglio , Cory Wajda , Kandabara Tapily , Takaaki Tsunomura , Takashi Ando , Paul C. Jamison , Eduard A. Cartier , Vijay Narayanan , Marinus J.P. Hopstaken
Abstract: A method of controlling the forming voltage of a dielectric film in a resistive random access memory (ReRAM) device. The method includes depositing a dielectric film contains intrinsic defects on a substrate, forming a plasma-excited treatment gas containing H2 gas, and exposing the dielectric film to the plasma-excited treatment gas to create additional defects in the dielectric film without substantially changing a physical thickness of the dielectric film, where the additional defects lower the forming voltage needed for generating an electrically conducting filament across the dielectric film. The dielectric film can include a metal oxide film and the plasma-excited treatment gas may be formed using a microwave plasma source.
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公开(公告)号：US10756194B2
公开(公告)日：2020-08-25
申请号：US16139795
申请日：2018-09-24
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Ruqiang Bao , Siddarth A. Krishnan , Unoh Kwon , Vijay Narayanan
IPC: H01L29/49 , H01L29/78 , H01L29/66 , H01L21/306 , H01L21/8238 , H01L21/84 , H01L27/092 , H01L27/12
Abstract: Semiconductor devices include at least one semiconductor fin in each of a first region and a second region. A first work function stack includes a bottom layer and a middle layer formed over the at least one semiconductor fin in the first region. A second work function stack includes a first layer and a second layer formed over the at least one semiconductor fin in the second region. The first layer is continuous with the bottom layer of the first work function stack and the second layer is continuous with the middle layer of the first work function stack, but has a smaller thickness than the middle layer.
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公开(公告)号：US10593600B2
公开(公告)日：2020-03-17
申请号：US15051804
申请日：2016-02-24
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Takashi Ando , Martin M. Frank , Renee T. Mo , Vijay Narayanan
IPC: H01L21/8258 , H01L27/092 , H01L21/8238 , H01L21/8252 , H01L29/267 , H01L29/66 , H01L29/10 , H01L29/51
Abstract: Semiconductor devices and methods of forming the same include forming a first channel region on a first semiconductor region. A second channel region is formed on a second semiconductor region. The second semiconductor region is formed from a semiconductor material that is different from a semiconductor material of the first semiconductor region. A semiconductor cap is formed on one or more of the first and second channel regions. A gate dielectric layer is formed over the nitrogen-containing layer. A gate is formed on the gate dielectric.
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85.发明申请公开(公告)号：US20200020595A1
公开(公告)日：2020-01-16
申请号：US16582440
申请日：2019-09-25
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
Inventor： Ruqiang Bao , Vijay Narayanan , Terence B. Hook , Hemanth Jagannathan
IPC: H01L21/8238 , H01L21/225 , H01L29/10 , H01L21/324 , H01L27/092 , H01L21/02 , H01L29/51
Abstract: A semiconductor device including pairs of multiple threshold voltage (Vt) devices includes at least a first region corresponding to a first pair of Vt devices, a second region corresponding to a second pair of Vt devices including a first dipole layer, and a third region corresponding to a third pair of Vt devices including a second dipole layer different from the first dipole layer.
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Patent Agency Ranking
86.发明申请公开(公告)号：US20200019732A1
公开(公告)日：2020-01-16
申请号：US16578321
申请日：2019-09-21
Applicant: International Business Machines Corporation
Inventor： Richard H. Boivie , Eduard A. Cartier , Daniel J. Friedman , Kohji Hosokawa , Charanjit Jutla , Wanki Kim , Chandrasekara Kothandaraman , Chung Lam , Frank R. Libsch , Seiji Munetoh , Ramachandran Muralidhar , Vijay Narayanan , Dirk Pfeiffer , Devendra K. Sadana , Ghavam G. Shahidi , Robert L. Wisnieff
Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
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公开(公告)号：US10529815B2
公开(公告)日：2020-01-07
申请号：US15799231
申请日：2017-10-31
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , ULVAC, Inc.
Inventor： Takashi Ando , Ruqiang Bao , Masanobu Hatanaka , Vijay Narayanan , Yohei Ogawa , John Rozen
IPC: H01L29/43 , H01L29/49 , H01L27/092 , H01L21/285 , H01L21/28 , H01L21/8238 , H01L29/66 , B82Y10/00 , H01L29/40 , H01L29/423 , H01L29/78 , H01L29/775 , H01L29/06
Abstract: A gate structure for effective work function adjustments of semiconductor devices that includes a gate dielectric on a channel region of a semiconductor device; a first metal nitride in direct contact with the gate dielectric; a conformal carbide of Aluminum material layer having an aluminum content greater than 30 atomic wt. %; and a second metal nitride layer in direct contact with the conformal aluminum (Al) and carbon (C) containing material layer. The conformal carbide of aluminum (Al) layer includes aluminum carbide, or Al4C3, yielding an aluminum (Al) content up to 57 atomic % (at. %) and work function setting from 3.9 eV to 5.0 eV at thicknesses below 25 Å. Such structures can present metal gate length scaling and resistance benefit below 25 nm compared to state of the art work function electrodes.
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公开(公告)号：US20190326387A1
公开(公告)日：2019-10-24
申请号：US16502783
申请日：2019-07-03
Applicant: International Business Machines Corporation
Inventor： Martin M. Frank , Takashi Ando , Xiao Sun , Jin Ping Han , Vijay Narayanan
IPC: H01L49/02 , H01B3/10 , H01L27/11507 , H01L21/02 , H01L21/3213 , H01L21/283
Abstract: Artificial synaptic devices with an HfO2-based ferroelectric layer that can be implemented in the CMOS back-end are provided. In one aspect, an artificial synapse element is provided. The artificial synapse element includes: a bottom electrode; a ferroelectric layer disposed on the bottom electrode, wherein the ferroelectric layer includes an HfO2-based material that crystallizes in a ferroelectric phase at a temperature of less than or equal to about 400° C.; and a top electrode disposed on the bottom electrode. An artificial synaptic device including the present artificial synapse element and methods for formation thereof are also provided.
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89.发明授权公开(公告)号：US10423805B2
公开(公告)日：2019-09-24
申请号：US15389078
申请日：2016-12-22
Applicant: International Business Machines Corporation
Inventor： Richard H. Boivie , Eduard A. Cartier , Daniel J. Friedman , Kohji Hosokawa , Charanjit Jutla , Wanki Kim , Chandrasekara Kothandaraman , Chung Lam , Frank R. Libsch , Seiji Munetoh , Ramachandran Muralidhar , Vijay Narayanan , Dirk Pfeiffer , Devendra K. Sadana , Ghavam G. Shahidi , Robert L. Wisnieff
Abstract: A private key of a public-private key pair with a corresponding identity is written to an integrated circuit including a processor, a non-volatile memory, and a cryptographic engine coupled to the processor and the non-volatile memory. The private key is written to the non-volatile memory. The integrated circuit is implemented in complementary metal-oxide semiconductor 14 nm or smaller technology. The integrated circuit is permanently modified, subsequent to the writing, such that further writing to the non-volatile memory is disabled and such that the private key can be read only by the cryptographic engine and not off-chip. Corresponding integrated circuits and wafers are also disclosed.
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公开(公告)号：US20190252500A1
公开(公告)日：2019-08-15
申请号：US16395084
申请日：2019-04-25
Applicant: International Business Machines Corporation
Inventor： Martin M. Frank , Takashi Ando , Xiao Sun , Jin Ping Han , Vijay Narayanan
IPC: H01L29/12 , H01L23/52 , H01L29/06 , H01L27/085
Abstract: Artificial synaptic devices with a HfO2-based ferroelectric layer that can be implemented in the CMOS front-end are provided. In one aspect, a method of forming a FET device is provided. The method includes: forming a shallow STI region in a substrate separating a first active area of the substrate from a second active area of the substrate; forming at least one FeFET on the substrate in the first active area having a ferroelectric material including a HfO2-based material; and forming at least one logic FET alongside the at least one FeFET on the substrate in the second active area, wherein the at least one logic FET has a gate dielectric including the HfO2-based material. A FET device formed by the present techniques is also provided.
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