公开(公告)号：US07872692B2

公开(公告)日：2011-01-18

申请号：US12056795

申请日：2008-03-27

申请人： Ahmed Y. Ginawi ,  Casey J. Grant ,  Christopher Ro ,  Sebastian T. Ventrone

发明人： Ahmed Y. Ginawi ,  Casey J. Grant ,  Christopher Ro ,  Sebastian T. Ventrone

IPC分类号： H04N5/50 ,  H04N5/44

CPC分类号： H04N7/163 ,  H04N21/4383 ,  H04N21/4394 ,  H04N21/44008 ,  H04N21/472 ,  H04N21/812

摘要： A design structure for systems for switching a displayed signal for a display between a plurality of signals are disclosed. In one embodiment, the design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, and includes: a system for switching a displayed signal for a display between a plurality of signals, the system including: a microcontroller; a chooser for setting a primary signal from a plurality of program-variable signals; a monitor tuner coupled to the microcontroller for tuning the primary signal during switching of the displayed signal from the primary signal to a secondary signal; a detector coupled to the monitor tuner and the microcontroller for detecting a predetermined condition in the primary signal; and a selector coupled to the microcontroller for switching the displayed signal from the secondary signal to the primary signal upon occurrence of the predetermined condition.

摘要翻译： 公开了用于在多个信号之间切换用于显示的显示信号的系统的设计结构。 在一个实施例中，设计结构体现在用于设计，制造或测试集成电路的机器可读介质中，并且包括：用于在多个信号之间切换用于显示的显示信号的系统，所述系统包括：微控制器 ; 用于从多个可编程信号设置主信号的选择器; 耦合到微控制器的监视器调谐器，用于在将所显示的信号从主信号切换到辅助信号期间调谐主信号; 耦合到所述监视器调谐器和所述微控制器的检测器，用于检测所述主信号中的预定条件; 以及耦合到微控制器的选择器，用于在发生预定条件时将显示的信号从次级信号切换到主信号。

公开(公告)号：US20100333058A1

公开(公告)日：2010-12-30

申请号：US12875517

申请日：2010-09-03

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

IPC分类号： G06F17/50

CPC分类号： G01R31/31718 ,  G11C17/14 ,  G11C29/88 ,  H03K19/17764 ,  H03K19/17796

摘要： A method for increasing the manufacturing yield of field programmable gate arrays (FPGAs) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.

摘要翻译： 一种提高现场可编程门阵列（FPGA）或其他可编程逻辑器件（PLD）的制造成品率的方法。 FPGA或其他PLD形成在几个部分中，每个部分都有自己的电源总线和输入/输出连接。 测试FPGA或其他PLD的每个部分，以识别FPGA或其他PLD中的缺陷。 FPGA或其他PLD根据该部分是否具有可接受的缺陷数量进行排序。 为FPGA或其他PLD芯片或部件分配的唯一编号将其识别为部分良好。 用于执行和配置FPGA或其他PLD的软件可以使用唯一编号仅对FPGA或其他PLD的已识别功能部分进行编程。 结果是产量增加，部分好的FPGA或其他PLD仍然可以被利用。

公开(公告)号：US20100269166A1

公开(公告)日：2010-10-21

申请号：US12621570

申请日：2009-11-19

申请人： Mariette Awad ,  Deanna C. Lim ,  Pascal A. Nsame ,  Dancyand J. Singley ,  Sebastian T. Ventrone

发明人： Mariette Awad ,  Deanna C. Lim ,  Pascal A. Nsame ,  Dancyand J. Singley ,  Sebastian T. Ventrone

IPC分类号： G06F21/20

CPC分类号： G06F21/55 ,  G06F21/31

摘要： In one embodiment, the invention is a method and apparatus for secure and reliable computing. One embodiment of an end-to-end security system for protecting a computing system includes a processor interface coupled to at least one of an application processor and an accelerator of the computing system, for receiving requests from the at least one of the application processor and the accelerator, a security processor integrating at least one embedded storage unit and connected to the processor interface with a tightly coupled memory unit for performing at least one of: authenticating, managing, monitoring, and processing the requests, and a data interface for communicating with a display, a network, and at least one embedded storage unit for securely holding at least one of data and programs used by the at least one of the application processor and the accelerator.

摘要翻译： 在一个实施例中，本发明是用于安全和可靠计算的方法和装置。 用于保护计算系统的端到端安全系统的一个实施例包括耦合到计算系统的应用处理器和加速器中的至少一个的处理器接口，用于接收来自应用处理器的至少一个和 加速器，集成至少一个嵌入式存储单元并且与处理器接口连接的紧密耦合的存储器单元的安全处理器，用于执行以下至少一个：认证，管理，监视和处理请求，以及数据接口，用于与 显示器，网络和至少一个嵌入式存储单元，用于安全地保持应用处理器和加速器中的至少一个使用的数据和程序中的至少一个。

公开(公告)号：US07793251B2

公开(公告)日：2010-09-07

申请号：US11275536

申请日：2006-01-12

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Paul S. Zuchowski

IPC分类号： G06F17/50

CPC分类号： G01R31/31718 ,  G11C17/14 ,  G11C29/88 ,  H03K19/17764 ,  H03K19/17796

摘要： A method for increasing the manufacturing yield of field programmable gate arrays (FPGAS) or other programmable logic devices (PLDs). An FPGA or other PLD is formed in several sections, each of the sections having its own power bus and input/output connections. Each section of the FPGA or other PLD is tested to identify defects in the FPGA or other PLD. The FPGA or other PLD is sorted according to whether the section has an acceptable number of defects. An assigned unique number for the FPGA or other PLD chip or part identifies it as partially good. Software for execution and configuring the FPGA or other PLD may use the unique number for programming only the identified functional sections of the FPGA or other PLD. The result is an increase in yield as partially good FPGAs or other PLDs may still be utilized.

摘要翻译： 一种提高现场可编程门阵列（FPGAS）或其他可编程逻辑器件（PLD）的制造成品率的方法。 FPGA或其他PLD形成在几个部分中，每个部分都有自己的电源总线和输入/输出连接。 测试FPGA或其他PLD的每个部分，以识别FPGA或其他PLD中的缺陷。 FPGA或其他PLD根据该部分是否具有可接受的缺陷数量进行排序。 为FPGA或其他PLD芯片或部件分配的唯一编号将其识别为部分良好。 用于执行和配置FPGA或其他PLD的软件可以使用唯一编号仅对FPGA或其他PLD的已识别功能部分进行编程。 结果是产量增加，部分好的FPGA或其他PLD仍然可以被利用。

公开(公告)号：US07765351B2

公开(公告)日：2010-07-27

申请号：US11684687

申请日：2007-03-12

申请人： Pascal A. Nsame ,  Anthony D. Polson ,  Nancy H. Pratt ,  Sebastian T. Ventrone

发明人： Pascal A. Nsame ,  Anthony D. Polson ,  Nancy H. Pratt ,  Sebastian T. Ventrone

IPC分类号： G06F12/00

CPC分类号： G06F9/526 ,  G06F9/544 ,  G06F15/167

摘要： A system and method for dynamically managing movement of semaphore data within the system. The system includes, but is no limited to, a plurality of functional units communicating over the network, a memory device communication with the plurality of functional units over the network, and at least one semaphore storage unit communicating with the plurality of functional unites and the memory device over the network. The plurality of functional units include a plurality of functional unit memory locations. The memory device includes a plurality of memory device memory locations. The at least one semaphore storage unit includes a plurality of semaphore storage unit memory locations. The at least one semaphore storage unit controls dynamic movement of the semaphore data among the plurality of functional unit memory locations, the plurality of memory device memory locations, the plurality of semaphore storage unit memory locations, and any combinations therof.

摘要翻译： 用于动态管理系统内信号量数据移动的系统和方法。 该系统包括但不限于通过网络通信的多个功能单元，与网络上的多个功能单元的存储设备通信，以及与多个功能单元通信的至少一个信号量存储单元，以及 存储设备通过网络。 多个功能单元包括多个功能单元存储单元。 存储器件包括多个存储器件存储器位置。 所述至少一个信号量存储单元包括多个信号量存储单元存储单元。 所述至少一个信号量存储单元控制所述多个功能单元存储器位置，所述多个存储器设备存储器位置，所述多个信号量存储单元存储器位置中的所述信号量数据的动态移动以及所述多个功能单元存储单元的任何组合。

公开(公告)号：US20090307637A1

公开(公告)日：2009-12-10

申请号：US12135250

申请日：2008-06-09

申请人： Susan K. Lichtensteiger ,  Michael R. Ouellette ,  Raymond W. M. Schuppe ,  Sebastian T. Ventrone

发明人： Susan K. Lichtensteiger ,  Michael R. Ouellette ,  Raymond W. M. Schuppe ,  Sebastian T. Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/72

摘要： Methods of designing and testing restore logic for restoring values to storage elements of power-managed logic circuitry. In one implementation, a design method disclosed includes providing a design of the logic circuitry that, when instantiated, will have a number of states it can be returned to upon repowering-up the logic circuitry. Values held by the storage elements are determined and utilized to categorize the storage elements into categories that allow the development of restore logic that will restore the state of the power-managed logic circuitry that is appropriate to the particular powering-up. The restore logic design is tested by modeling it and the power-managed logic circuitry in a hardware description language and simulating the number of states over a number of test cases. If the design and testing are successful, the restore logic can be optimized for instantiation into an actual integrated circuit.

摘要翻译： 设计和测试还原逻辑的方法，用于将功能管理逻辑电路的存储元件恢复为值。 在一个实施方式中，所公开的设计方法包括提供逻辑电路的设计，当被实例化时，逻辑电路将具有多个状态，可以在重新启动逻辑电路时将其返回。 由存储元件保存的值被确定并用于将存储元件分类成允许开发还原逻辑的类别，恢复逻辑将恢复适合于特定供电的功率管理逻辑电路的状态。 恢复逻辑设计通过对硬件描述语言进行建模和功耗管理的逻辑电路进行测试，并通过多个测试用例模拟状态数量。 如果设计和测试成功，则可以将恢复逻辑优化为实例化为实际的集成电路。

公开(公告)号：US20090239313A1

公开(公告)日：2009-09-24

申请号：US12343686

申请日：2008-12-24

申请人： Theodoros Anemikos ,  Ezra D.B. Hall ,  Sebastian T. Ventrone

发明人： Theodoros Anemikos ,  Ezra D.B. Hall ,  Sebastian T. Ventrone

IPC分类号： G06F17/50 ,  H01L21/66

CPC分类号： G06F17/5045 ,  G01R31/2884 ,  G01R31/3025 ,  G06F2217/12 ,  H01L2924/0002 ,  Y02P90/265 ,  H01L2924/00

摘要： Disclosed are embodiments of a design and manufacturing system and an associated method that allow for design analysis and for insertion, during wafer manufacture, of intra-process monitoring circuitry. These embodiments use a library of pre-qualified intra-process monitoring circuits and a cross-correlation table that links different monitoring circuits with different IC chip components. Specifically, these embodiments analyze integrated circuit chip design data to identify the components designed into the chip. Then, one or more intra-process monitoring circuits are selected from the library and the design data is modified to include the selected monitoring circuit(s).

摘要翻译： 公开了设计和制造系统以及相关方法的实施例，其允许在晶片制造期间进行设计分析和插入过程内监控电路。 这些实施例使用预定义的内部过程监视电路库和将不同监控电路与不同IC芯片组件链接的互相关表。 具体地，这些实施例分析集成电路芯片设计数据以识别设计到芯片中的部件。 然后，从库中选择一个或多个进程内监控电路，并且修改设计数据以包括所选择的监视电路。

公开(公告)号：US07489163B2

公开(公告)日：2009-02-10

申请号：US11869921

申请日：2007-10-10

申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Jack R. Smith ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G06F7/38 ,  H03K19/177

CPC分类号： H03K19/17776 ,  H03K19/17732 ,  H03K19/17756 ,  H03K19/17772

摘要： A field programmable gate array (FPGA) device including a non-non-programming-based default power-on electronic configuration. The non-non-programming-based default power-on electronic configuration defines a default state to initial a first logic function. Upon power-up, the FPGA device would be enabled to enter the default state without having first to be configured via a conventional programming mode, thus saving precious processing time during power-up. Several embodiments are disclosed, such as a mask via circuit, an asynchronized set/reset circuit, an unbalanced latch circuit and a flush and scan circuit. A related method is also disclosed to reduce the memory size dedicated to the first logic function to facilitate further programming after power-up. In addition to time saving and further programming, the FPGA device can also allow partial or incremental programming to expand the full functionality to match customer's different needs.

摘要翻译： 包括非基于非编程的默认开机电子配置的现场可编程门阵列（FPGA）设备。 非基于非编程的默认开机电子配置定义了初始化第一逻辑功能的默认状态。 上电时，FPGA器件将能够进入默认状态，而不必首先通过常规编程模式进行配置，从而在上电时节省宝贵的处理时间。 公开了几个实施例，例如掩模通孔电路，异步设置/复位电路，不平衡锁存电路和冲洗和扫描电路。 还公开了一种相关方法，以减少专用于第一逻辑功能的存储器大小，以便在上电之后进一步编程。 除了节省时间和进一步的编程之外，FPGA器件还可以允许部分或增量编程扩展完整的功能以满足客户的不同需求。

公开(公告)号：US07469395B2

公开(公告)日：2008-12-23

申请号：US11952544

申请日：2007-12-07

申请人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

发明人： John M. Cohn ,  Alvar A. Dean ,  Amir H. Farrahi ,  David J. Hathaway ,  Thomas M. Lepsic ,  Jagannathan Narasimhan ,  Scott A. Tetreault ,  Sebastian T. Ventrone

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5022 ,  G06F17/5077

摘要： An electrical wiring structure and a computer system for designing the electrical wiring structure. The electrical wiring structure includes a wire pair. The wire pair includes a first wire and a second wire. The second wire is slated for being tri-stated. The wire pair has a same-direction switching probability φSD per clock cycle that is no less than a pre-selected minimum same-direction switching probability φSD,MIN or has an opposite-direction switching probability φOD per clock cycle that is no less than a pre-selected minimum opposite-direction switching probability φOD,MIN. The first wire and the second wire satisfies at least one mathematical relationship involving LCOMMON and WSPACING, where WSPACING is defined as a spacing between the first wire and the second wire, and LCOMMON is defined as a common run length of the first wire and the second wire.

摘要翻译： 一种用于设计电气布线结构的电气布线结构和计算机系统。 电气配线结构包括电线对。 线对包括第一线和第二线。 第二根电线被预定为三态。 线对具有每时钟周期相同方向的切换概率phiSD，其不小于预先选择的最小相同方向切换概率phiSD，MIN或具有不小于a的每个时钟周期的相反方向切换概率phiOD 预先选择的最小相反方向切换概率phiOD，MIN。 第一线和第二线满足涉及LCOMMON和WSPACING的至少一个数学关系，其中WSPACING被定义为第一线和第二线之间的间隔，并且LCOMMON被定义为第一线和第二线的公共行程长度 线。

公开(公告)号：US20080285338A1

公开(公告)日：2008-11-20

申请号：US12180776

申请日：2008-07-28

申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

IPC分类号： G11C11/34

CPC分类号： G11C11/417

摘要： A system, method and program product for determining a history state of data in a data retaining device are disclosed. A state of a partially-depleted silicon-on-insulator (PD SOI) device coupled to a data retaining device is measured to indicate a body voltage of the PD SOI device. The body voltage of the PD SOI device may indicate, among others, how long the PD SOI device has been idling, which indirectly indicates how long data in the data retaining device has not been accessed. As such, the current invention may be used efficiently with, e.g., a cache replacement algorithm in a management of the data retaining device.

摘要翻译： 公开了一种用于确定数据保持装置中的数据的历史状态的系统，方法和程序产品。 耦合到数据保持装置的部分耗尽的绝缘体上硅（PD SOI）器件的状态被测量以指示PD SOI器件的体电压。 PD SOI器件的体电压可以指示PD SOI器件已经空转多长时间，这间接地指示数据保持器件中的数据未被访问多长时间。 因此，本发明可以在数据保留装置的管理中与例如高速缓存替换算法有效地使用。