公开(公告)号：US20230420559A1

公开(公告)日：2023-12-28

申请号：US18466039

申请日：2023-09-13

Applicant: Infineon Technologies AG

Inventor： Dethard Peters ,  Sascha Axel Baier ,  Tomas Reiter ,  Sandeep Walia ,  Frank Wolter

IPC: H01L29/78 ,  G01R31/52 ,  G01K7/16 ,  G01R31/26 ,  G01R31/27 ,  G01R31/28 ,  H01L29/16

CPC classification number: H01L29/7815 ,  G01R31/52 ,  G01K7/16 ,  G01R31/2628 ,  G01R31/27 ,  G01R31/2831 ,  H01L29/1608 ,  H01L29/7805 ,  H01L29/7813

Abstract: A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source regions of the current sense transistor. The doped resistor region has an opposite conductivity type as the source regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

公开(公告)号：US20230094032A1

公开(公告)日：2023-03-30

申请号：US18073860

申请日：2022-12-02

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Thomas Basler ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Michael Hell ,  Jens Peter Konrath ,  Shiqin Niu ,  Dethard Peters ,  Konrad Schraml ,  Bernd Leonhard Zippelius

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: A method of producing a silicon carbide (SiC) device includes: forming a stripe-shaped trench gate structure that extends from a first surface of a SiC body into the SiC body, the gate structure having a gate length along a lateral first direction, a bottom surface and a first gate sidewall of the gate structure being connected via a first bottom edge of the gate structure; forming at least one source region of a first conductivity type; and forming a shielding region of a second conductivity type in contact with the first bottom edge of the gate structure across at least 20% of the gate length. Forming the shielding region includes: forming a deep shielding portion; and forming a top shielding portion between the first surface and the deep shielding portion, the top shielding portion being in contact with the first bottom edge.

公开(公告)号：US11552173B2

公开(公告)日：2023-01-10

申请号：US16986338

申请日：2020-08-06

Applicant: Infineon Technologies AG

Inventor： Caspar Leendertz ,  Thomas Basler ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Michael Hell ,  Jens Peter Konrath ,  Shiqin Niu ,  Dethard Peters ,  Konrad Schraml ,  Bernd Leonhard Zippelius

IPC: H01L29/16 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78

Abstract: A silicon carbide device includes a stripe-shaped trench gate structure extending from a first surface into a silicon carbide body. The gate structure has a gate length along a lateral first direction. A bottom surface and an active first gate sidewall of the gate structure are connected via a first bottom edge of the gate structure. The silicon carbide device further includes at least one source region of a first conductivity type. A shielding region of a second conductivity type is in contact with the first bottom edge of the gate structure across at least 20% of the gate length.

公开(公告)号：US11444155B2

公开(公告)日：2022-09-13

申请号：US17316178

申请日：2021-05-10

Applicant: Infineon Technologies AG

Inventor： Andreas Huerner ,  Dethard Peters

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/16 ,  H01L29/78

Abstract: A silicon carbide semiconductor device includes a first load electrode disposed on a first surface of a silicon carbide semiconductor body, a first doped region disposed in the silicon carbide semiconductor body and electrically connected to the first load electrode, and an insulated gate field effect transistor electrically connected in series with the first doped region, the insulated gate field effect transistor including a source region and a body region, the body region being electrically connected to the first load electrode, wherein a geometry and dopant concentration of the first doped region is such that a resistance of the first doped region increases by at least a factor of two as load current in the insulated gate field effect transistor rises.

公开(公告)号：US20220271156A1

公开(公告)日：2022-08-25

申请号：US17181408

申请日：2021-02-22

Applicant: Infineon Technologies AG

Inventor： Dethard Peters ,  Sascha Axel Baier ,  Tomas Manuel Reiter ,  Sandeep Walia ,  Frank Wolter

IPC: H01L29/78 ,  H01L29/16 ,  G01R31/28 ,  G01R31/52 ,  G01R31/26 ,  G01K7/16 ,  G01R31/27

Abstract: A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source and body regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source and body regions of the current sense transistor. The doped resistor region has a same conductivity type as the body regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

公开(公告)号：US11245007B2

公开(公告)日：2022-02-08

申请号：US15979218

申请日：2018-05-14

Applicant: Infineon Technologies AG

Inventor： Dethard Peters

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/45 ,  H01L23/00 ,  H01L29/417 ,  H01L29/16 ,  H01L29/49 ,  H01L29/739 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor body of a wide-bandgap semiconductor material. A plurality of first bond areas is connected to a first load terminal of the semiconductor device. First gate fingers are arranged between the first bond areas. The first gate fingers extend in a first lateral direction and branch off from at least one of a first gate line portion and a second gate line portion. Second gate fingers extend in the first lateral direction. A first length of any of the first gate fingers along the first lateral direction is greater than a second length of any of the second gate fingers along the first lateral direction. A sum of the first length and the second length is equal to or greater than a lateral distance between the first gate line portion and the second gate line portion along the first lateral direction.

公开(公告)号：US20210104605A1

公开(公告)日：2021-04-08

申请号：US16595375

申请日：2019-10-07

Applicant: Infineon Technologies AG

Inventor： Michael Hell ,  Rudolf Elpelt ,  Caspar Leendertz ,  Dethard Peters

IPC: H01L29/167 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

Abstract: A SiC substrate of a semiconductor device includes: a drift region of a first conductivity type; a body region of a second conductivity type having a channel region which adjoins a first surface of the SiC substrate; a source region of the first conductivity type adjoining a first end of the channel region; an extension region of the first conductivity type at an opposite side of the body region as the source region and vertically extending to the drift region; a buried region of the second conductivity type below the body region and having a tail which extends toward the first surface and adjoins the extension region; and a compensation region of the first conductivity type protruding from the extension region into the body region along the first surface and terminating at a second end of the channel region opposite the first end.

公开(公告)号：US10896952B2

公开(公告)日：2021-01-19

申请号：US16797463

申请日：2020-02-21

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Romain Esteve ,  Florian Grasse ,  Caspar Leendertz ,  Shiqin Niu ,  Dethard Peters ,  Ralf Siemieniec ,  Bernd Zippelius

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088

Abstract: A semiconductor device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. A trench interval which defines a space between adjacent gate trenches extends in a second direction perpendicular to the first direction. Source regions of a first conductivity type formed in the SiC substrate occupy a first part of the space between adjacent gate trenches. Body regions of a second conductivity type opposite the first conductivity type formed in the SiC substrate and below the source regions occupy a second part of the space between adjacent gate trenches. Body contact regions of the second conductivity type formed in the SiC substrate occupy a third part of the space between adjacent gate trenches. Shielding regions of the second conductivity type formed deeper in the SiC substrate than the body regions adjoin a bottom of at least some of the gate trenches.

公开(公告)号：US10700182B2

公开(公告)日：2020-06-30

申请号：US15979050

申请日：2018-05-14

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Romain Esteve ,  Daniel Kueck ,  Dethard Peters ,  Ralf Siemieniec ,  Bernd Zippelius

IPC: G06F30/398 ,  H01L29/66 ,  H01L29/739 ,  H01L27/02 ,  H01L29/16 ,  H01L29/78 ,  H01L29/861 ,  H01L21/66

Abstract: By using at least one of a processor device and model transistor cells, a set of design parameters for at least one of a transistor cell and a drift structure of a wide band-gap semiconductor device is determined, wherein an on state failure-in-time rate and an off state failure-in-time rate of a gate dielectric of the transistor cell are within a same order of magnitude for a predefined on-state gate-to-source voltage, a predefined off-state gate-to-source voltage, and a predefined off-state drain-to-source voltage.

公开(公告)号：US10586845B1

公开(公告)日：2020-03-10

申请号：US16193296

申请日：2018-11-16

Applicant: Infineon Technologies AG

Inventor： Thomas Aichinger ,  Wolfgang Bergner ,  Paul Ellinghaus ,  Rudolf Elpelt ,  Romain Esteve ,  Florian Grasse ,  Caspar Leendertz ,  Shiqin Niu ,  Dethard Peters ,  Ralf Siemieniec ,  Bernd Zippelius

IPC: H01L29/06 ,  H01L29/16 ,  H01L21/265 ,  H01L29/423 ,  H01L29/66 ,  H01L27/088

Abstract: According to an embodiment of a semiconductor device, the device includes gate trenches formed in a SiC substrate and extending lengthwise in parallel in a first direction. Rows of source regions of a first conductivity type are formed in the SiC substrate and extend lengthwise in parallel in a second direction which is transverse to the first direction. Rows of body regions of a second conductivity type opposite the first conductivity type are formed in the SiC substrate below the rows of source regions. Rows of body contact regions of the second conductivity type are formed in the SiC substrate. The rows of body contact regions extend lengthwise in parallel in the second direction. First shielding regions of the second conductivity type are formed deeper in the SiC substrate than the rows of body regions.