公开(公告)号：US12132104B2

公开(公告)日：2024-10-29

申请号：US18466039

申请日：2023-09-13

Applicant: Infineon Technologies AG

Inventor： Dethard Peters ,  Sascha Axel Baier ,  Tomas Reiter ,  Sandeep Walia ,  Frank Wolter

IPC: H01L29/78 ,  G01K7/16 ,  G01R31/26 ,  G01R31/27 ,  G01R31/28 ,  G01R31/52 ,  H01L29/16

CPC classification number: H01L29/7815 ,  G01K7/16 ,  G01R31/2628 ,  G01R31/27 ,  G01R31/2831 ,  G01R31/52 ,  H01L29/1608 ,  H01L29/7805 ,  H01L29/7813

Abstract: A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source regions of the current sense transistor. The doped resistor region has an opposite conductivity type as the source regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

公开(公告)号：US20170170028A1

公开(公告)日：2017-06-15

申请号：US15379243

申请日：2016-12-14

Applicant: Infineon Technologies AG

Inventor： Werner Schustereder ,  Helmut Oefner ,  Hans-Joachim Schulze ,  Sandeep Walia

IPC: H01L21/322 ,  H01L21/02 ,  H01L21/306 ,  H01L21/223

CPC classification number: H01L21/3225 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/30604

Abstract: Disclosed is a method for processing a semiconductor wafer. The method includes forming an oxygen containing region in the semiconductor wafer, wherein forming the oxygen containing region includes introducing oxygen via a first surface into the semiconductor wafer. The method further includes creating vacancies at least in the oxygen containing region and annealing at least the oxygen containing region in an annealing process so as to form oxygen precipitates.

公开(公告)号：US20240096934A1

公开(公告)日：2024-03-21

申请号：US17945467

申请日：2022-09-15

Applicant: Infineon Technologies AG

Inventor： Paul ELLINGHAUS ,  Sandeep Walia

IPC: H01L29/06 ,  H01L21/04 ,  H01L29/10 ,  H01L29/16 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/063 ,  H01L21/0465 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068 ,  H01L29/7813

Abstract: According to some embodiments, a method for manufacturing a semiconductor device is provided. One or more first implantation processes are performed to form an implanted region, of a first conductivity type, in a semiconductor body. A trench is formed in the semiconductor body. After forming the trench, a second implantation process is performed to form a current spread region, of a second conductivity type, in the semiconductor body. The second implantation process includes implanting first dopants, through a top surface of the semiconductor body, to form a first portion of the current spread region, and implanting second dopants, through a bottom of the trench, to form a second portion of the current spread region. A gate structure is formed in the trench. A vertical position of the first portion of the current spread region matches a vertical position of the gate structure. The second portion of the current spread region underlies the gate structure.

公开(公告)号：US11799026B2

公开(公告)日：2023-10-24

申请号：US17181408

申请日：2021-02-22

Applicant: Infineon Technologies AG

Inventor： Dethard Peters ,  Sascha Axel Baier ,  Tomas Manuel Reiter ,  Sandeep Walia ,  Frank Wolter

IPC: H01L29/78 ,  G01R31/52 ,  G01K7/16 ,  G01R31/26 ,  G01R31/27 ,  G01R31/28 ,  H01L29/16

CPC classification number: H01L29/7815 ,  G01K7/16 ,  G01R31/2628 ,  G01R31/27 ,  G01R31/2831 ,  G01R31/52 ,  H01L29/1608 ,  H01L29/7805 ,  H01L29/7813

Abstract: A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source and body regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source and body regions of the current sense transistor. The doped resistor region has a same conductivity type as the body regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

公开(公告)号：US20230420559A1

公开(公告)日：2023-12-28

申请号：US18466039

申请日：2023-09-13

Applicant: Infineon Technologies AG

Inventor： Dethard Peters ,  Sascha Axel Baier ,  Tomas Reiter ,  Sandeep Walia ,  Frank Wolter

IPC: H01L29/78 ,  G01R31/52 ,  G01K7/16 ,  G01R31/26 ,  G01R31/27 ,  G01R31/28 ,  H01L29/16

CPC classification number: H01L29/7815 ,  G01R31/52 ,  G01K7/16 ,  G01R31/2628 ,  G01R31/27 ,  G01R31/2831 ,  H01L29/1608 ,  H01L29/7805 ,  H01L29/7813

Abstract: A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source regions of the current sense transistor. The doped resistor region has an opposite conductivity type as the source regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

公开(公告)号：US20220271156A1

公开(公告)日：2022-08-25

申请号：US17181408

申请日：2021-02-22

Applicant: Infineon Technologies AG

Inventor： Dethard Peters ,  Sascha Axel Baier ,  Tomas Manuel Reiter ,  Sandeep Walia ,  Frank Wolter

IPC: H01L29/78 ,  H01L29/16 ,  G01R31/28 ,  G01R31/52 ,  G01R31/26 ,  G01K7/16 ,  G01R31/27

Abstract: A semiconductor die includes: a SiC substrate; power and current sense transistors integrated in the substrate such that the current sense transistor mirrors current flow in the main power transistor; a gate terminal electrically connected to gate electrodes of both transistors; a drain terminal electrically connected to a drain region in the substrate and which is common to both transistors; a source terminal electrically connected to source and body regions of the power transistor; a dual mode sense terminal; and a doped resistor region in the substrate between the transistors. The dual mode sense terminal is electrically connected to source and body regions of the current sense transistor. The doped resistor region has a same conductivity type as the body regions of both transistors and is configured as a temperature sense resistor that electrically connects the source terminal to the dual mode sense terminal.

公开(公告)号：US09934988B2

公开(公告)日：2018-04-03

申请号：US15379243

申请日：2016-12-14

Applicant: Infineon Technologies AG

Inventor： Werner Schustereder ,  Helmut Oefner ,  Hans-Joachim Schulze ,  Sandeep Walia

IPC: H01L21/322 ,  H01L21/02 ,  H01L21/223 ,  H01L21/306 ,  H01L21/265

CPC classification number: H01L21/3225 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/2236 ,  H01L21/26506 ,  H01L21/30604

Abstract: Disclosed is a method for processing a semiconductor wafer. The method includes forming an oxygen containing region in the semiconductor wafer, wherein forming the oxygen containing region includes introducing oxygen via a first surface into the semiconductor wafer. The method further includes creating vacancies at least in the oxygen containing region and annealing at least the oxygen containing region in an annealing process so as to form oxygen precipitates.