-
公开(公告)号：US08842412B2
公开(公告)日：2014-09-23
申请号：US14176460
申请日：2014-02-10
摘要： A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.
-
公开(公告)号：US08649153B2
公开(公告)日：2014-02-11
申请号：US13096850
申请日：2011-04-28
IPC分类号： H01G4/30
摘要： A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.
摘要翻译： 描述了一种片式电容器和互连布线，其集成了金属绝缘体金属（MIM）电容器，锥形通孔和通孔，其在集成电路中耦合到电容器的顶部和底部电极中的一个或两个。 描述了有形地体现在机器可读介质中的设计结构，其包括在集成电路中定义MIM电容器，锥形通孔，通孔和布线电平的计算机可读代码。
-
83.发明申请LOCAL WIRING FOR A BIPOLAR JUNCTION TRANSISTOR INCLUDING A SELF-ALIGNED EMITTER REGION 有权用于包括自对准发射极区域的双极晶体管的本地布线公开(公告)号：US20140021587A1
公开(公告)日：2014-01-23
申请号：US13551971
申请日：2012-07-18
申请人： David L. Harame , Zhong-Xiang He , Qizhi Liu
发明人： David L. Harame , Zhong-Xiang He , Qizhi Liu
CPC分类号： H01L29/66234 , H01L29/0804 , H01L29/66287 , H01L29/73 , H01L29/732
摘要： Aspects of the invention provide for a bipolar transistor of a self-aligned emitter. In one embodiment, the invention provides a method of forming local wiring for a bipolar transistor with a self-aligned sacrificial emitter, including: performing an etch to remove the sacrificial emitter to form an emitter opening between two nitride spacers; depositing an in-situ doped emitter into the emitter opening; performing a recess etch to partially remove a portion of the in-situ doped emitter; depositing a silicon dioxide layer over the recessed in-situ doped emitter; planarizing the silicon dioxide layer via chemical mechanical polishing; etching an emitter trench over the recessed in-situ doped emitter; and depositing tungsten and forming a tungsten wiring within the emitter trench via chemical mechanical polishing.
摘要翻译： 本发明的方面提供了一种自对准发射极的双极晶体管。 在一个实施例中，本发明提供了一种用于具有自对准牺牲发射器的双极晶体管的局部布线的方法，包括：执行蚀刻以去除牺牲发射极以在两个氮化物间隔物之间形成发射极开口; 将原位掺杂的发射体沉积到发射极开口中; 执行凹陷蚀刻以部分去除原位掺杂发射体的一部分; 在凹入的原位掺杂发射体上沉积二氧化硅层; 通过化学机械抛光使二氧化硅层平坦化; 在凹入的原位掺杂发射体上蚀刻发射极沟槽; 并通过化学机械抛光沉积钨并在发射器沟槽内形成钨布线。
-
84.发明授权On chip shielding structure for integrated circuits or devices on a substrate and method of shielding 有权用于集成电路或基板上的器件的片上屏蔽结构和屏蔽方法公开(公告)号：US08589832B2
公开(公告)日：2013-11-19
申请号：US11844397
申请日：2007-08-24
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Xuefeng Liu
IPC分类号： G06F17/50
CPC分类号： H05K9/0022
摘要： An electromagnetic shielding structure that includes a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate. At least one feed through device is associated with the conductive structure and provides signals to the circuit or circuit device. The method includes forming a shielding structure so that the shielding structure at least one of is at least partially arranged within the substrate and surrounds the circuit or circuit device and associating at least one feed through device with the shielding structure.
摘要翻译： 一种电磁屏蔽结构，其包括围绕并容纳布置在基板上的电路或电路装置的导电结构。 至少一个馈送装置与导电结构相关联，并向电路或电路装置提供信号。 所述方法包括形成屏蔽结构，使得所述屏蔽结构至少部分地至少部分地布置在所述基板内并且围绕所述电路或电路装置并且将至少一个馈送装置与所述屏蔽结构相关联。
-
公开(公告)号：US08519892B2
公开(公告)日：2013-08-27
申请号：US13534350
申请日：2012-06-27
申请人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
发明人： Hanyi Ding , Kai D. Feng , Zhong-Xiang He , Zhenrong Jin , Xuefeng Liu
CPC分类号： H01Q1/2283 , H01Q1/40 , H01Q9/26 , H01Q9/285 , H01Q19/108 , H01Q19/30
摘要： A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.
摘要翻译： 提供集成收发器，天线和接收器的半导体芯片。 收发器位于半导体衬底的前侧。 通过基底通孔提供收发器和位于半导体衬底背面的接收器之间的电连接。 连接到收发器的天线位于位于基板正面的电介质层中。 反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。 可以采用贯穿衬底电介质通孔的阵列来降低天线和反射板之间材料的有效介电常数，由此减小毫米波的波长并提高辐射效率。 还提供了用于设计，制造或测试这种半导体芯片的设计的设计结构。
-
公开(公告)号：US20120275080A1
公开(公告)日：2012-11-01
申请号：US13096850
申请日：2011-04-28
摘要： A chip capacitor and interconnecting wiring is described incorporating a metal insulator metal (MIM) capacitor, tapered vias and vias coupled to one or both of the top and bottom electrodes of the capacitor in an integrated circuit. A design structure tangibly embodied in a machine readable medium is described incorporating computer readable code defining a MIM capacitor, tapered vias, vias and wiring levels in an integrated circuit.
摘要翻译： 描述了一种片式电容器和互连布线，其集成了金属绝缘体金属（MIM）电容器，锥形通孔和通孔，其在集成电路中耦合到电容器的顶部和底部电极中的一个或两个。 描述了有形地体现在机器可读介质中的设计结构，其包括在集成电路中定义MIM电容器，锥形通孔，通孔和布线电平的计算机可读代码。
-
87.发明授权公开(公告)号：US08298902B2
公开(公告)日：2012-10-30
申请号：US12634742
申请日：2009-12-10
IPC分类号： H01L21/20
CPC分类号： H01L21/76885 , H01L21/76816 , H01L21/76832 , H01L21/76834 , H01L27/016 , H01L28/20 , H01L28/40
摘要： Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.
摘要翻译： 包括诸如薄膜电阻器或金属 - 绝缘体 - 金属（MIM）电容器的无源元件的互连结构，用于制造包括无源元件的互连结构的方法，以及体现在机器可读介质中的设计结构，用于设计， 制造或测试诸如射频集成电路的集成电路。 电介质层的顶表面相对于电介质层中导电特征的顶表面凹陷。 无源元件形成在介电层的凹入的顶表面上，并且包括与导电特征的顶表面共面或低于导电特征的顶表面的导电材料层。
-
公开(公告)号：US20120218030A1
公开(公告)日：2012-08-30
申请号：US13034758
申请日：2011-02-25
申请人： Fen Chen , Kai D. Feng , Zhong-Xiang He
发明人： Fen Chen , Kai D. Feng , Zhong-Xiang He
IPC分类号： H03K19/003
CPC分类号： H03K19/00307
摘要： Managing reliability of a circuit that includes a plurality of duplicate components, with less than all of the components being active at any time during circuit operation, where reliability is managed by operating, by the circuit, with a first set of components that includes a predefined number of components; selecting, without altering circuit performance and in accordance with a circuit reliability protocol, a second set of components with which to operate, including activating an inactive component and deactivating an active component of the first set of components; and operating, by the circuit, with the second set of components.
摘要翻译： 管理包括多个重复部件的电路的可靠性，其中小于所有组件在电路操作期间的任何时间处于活动状态，其中可靠性由电路通过第一组组件来管理，该组件包括预定义的 组件数量; 根据电路可靠性协议选择不改变电路性能的第二组组件，包括激活非活动组件和去激活第一组组件的活动组件; 并通过电路与第二组元件一起操作。
-
89.发明授权Structure and design structure for high-Q value inductor and method of manufacturing the same 有权高Q值电感器的结构和设计结构及其制造方法公开(公告)号：US08232173B2
公开(公告)日：2012-07-31
申请号：US12917029
申请日：2010-11-01
申请人： Hanyi Ding , Mete Erturk , Robert A. Groves , Zhong-Xiang He , Peter J. Lindgren , Anthony K. Stamper
发明人： Hanyi Ding , Mete Erturk , Robert A. Groves , Zhong-Xiang He , Peter J. Lindgren , Anthony K. Stamper
IPC分类号： H01L21/20
CPC分类号： H01L28/10 , H01L21/76898 , H01L23/5227 , H01L2924/0002 , H01L2924/0001 , H01L2924/00
摘要： Structures with high-Q value inductors, design structure for high-Q value inductors and methods of fabricating such structures is disclosed herein. A method in a computer-aided design system for generating a functional design model of an inductor is also provided. The method includes: generating a functional representation of a plurality of vertical openings simultaneously formed in a substrate, wherein a first of the plurality of vertical openings is used as through silicon vias and is etched deeper than a second of the plurality of vertical openings used for high-Q inductors; generating a functional representation of a dielectric layer formed in the plurality of vertical openings; and generating a functional representation of a metal layer deposited on the dielectric layer in the plurality of vertical.
摘要翻译： 具有高Q值电感器的结构，高Q值电感器的设计结构和制造这种结构的方法在本文中公开。 还提供了一种用于产生电感器的功能设计模型的计算机辅助设计系统中的方法。 该方法包括：产生同时形成在衬底中的多个垂直开口的功能性表示，其中多个垂直开口中的第一个用作通过硅通孔，并且被蚀刻比用于多个垂直开口的多个垂直开口中的第二个 高Q电感; 产生形成在所述多个垂直开口中的电介质层的功能性表示; 以及生成沉积在所述多个垂直方向上的所述电介质层上的金属层的功能表示。
-
90.发明授权Complimentary metal-insulator-metal (MIM) capacitors and method of manufacture 有权免费金属绝缘体金属（MIM）电容器和制造方法公开(公告)号：US08191217B2
公开(公告)日：2012-06-05
申请号：US12535769
申请日：2009-08-05
IPC分类号： H01G7/00
CPC分类号： H01G4/33 , H01G4/1209 , H01G4/232 , H01G4/38 , H01L23/5223 , H01L27/0805 , H01L28/40 , H01L28/60 , H01L2924/0002 , Y10T29/43 , Y10T29/435 , Y10T29/49156 , H01L2924/00
摘要： A high density capacitor and low density capacitor simultaneously formed on a single wafer and a method of manufacture is provided. The method includes depositing a bottom plate on a dielectric material; depositing a low-k dielectric on the bottom plate; depositing a high-k dielectric on the low-k dielectric and the bottom plate; depositing a top plate on the high-k dielectric; and etching a portion of the bottom plate and the high-k dielectric to form a first metal-insulator-metal (MIM) capacitor having a dielectric stack with a first thickness and a second MIM capacitor having a dielectric stack with a second thickness different than the first thickness.
摘要翻译： 同时形成在单个晶片上的高密度电容器和低密度电容器和制造方法。 该方法包括在电介质材料上沉积底板; 在底板上沉积低k介质; 在低k电介质和底板上沉积高k电介质; 在高k电介质上沉积顶板; 以及蚀刻所述底板和所述高k电介质的一部分以形成具有第一厚度的电介质堆叠的第一金属 - 绝缘体金属（MIM）电容器和具有不同于第二厚度的第二厚度的电介质叠层的第二MIM电容器 第一厚度。
-
-
-
-
-
-
-
-
-
搜索结果
222 条记录 (耗时 0.035 秒)