公开(公告)号：US20150117110A1

公开(公告)日：2015-04-30

申请号：US14528915

申请日：2014-10-30

申请人： Zhijiong Luo

发明人： Zhijiong Luo

IPC分类号： H01L29/788 ,  H01L27/115 ,  H01L29/66 ,  G11C16/26

CPC分类号： H01L29/66825 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/4234 ,  H01L29/7881

摘要： Technologies are generally related to a connecting storage gate memory device, system, and method of manufacture.

摘要翻译： 技术通常与连接存储门存储器件，系统和制造方法相关。

公开(公告)号：US08969930B2

公开(公告)日：2015-03-03

申请号：US13321886

申请日：2011-04-06

申请人： Haizhoou Yin ,  Zhijiong Luo ,  Huilong Zhu

发明人： Haizhoou Yin ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L29/66

CPC分类号： H01L21/28247 ,  H01L29/66545 ,  H01L29/78

摘要： A gate stack structure comprises an isolation dielectric layer formed on and embedded into a gate. A sidewall spacer covers opposite side faces of the isolation dielectric layer, and the isolation dielectric layer located on an active region is thicker than the isolation dielectric layer located on a connection region. A method for manufacturing the gate stack structure comprises removing part of the gate in thickness, the thickness of the removed part of the gate on the active region is greater than the thickness of the removed part of the gate on the connection region so as to expose opposite inner walls of the sidewall spacer; forming an isolation dielectric layer on the gate to cover the exposed inner walls. There is also provided a semiconductor device and a method for manufacturing the same. The methods can reduce the possibility of short-circuit occurring between the gate and the second contact hole and can be compatible with the dual-contact-hole process.

摘要翻译： 栅极堆叠结构包括形成在栅极上并嵌入栅极中的隔离电介质层。 侧壁间隔物覆盖隔离电介质层的相对侧面，并且位于有源区上的隔离电介质层比位于连接区上的隔离电介质层厚。 一种用于制造栅极堆叠结构的方法包括去除栅极的一部分厚度，有源区上的栅极的去除部分的厚度大于连接区域上的栅极的去除部分的厚度，以便露出 侧壁间隔件的相对的内壁; 在栅极上形成隔离电介质层以覆盖暴露的内壁。 还提供了一种半导体器件及其制造方法。 该方法可以降低栅极和第二接触孔之间发生短路的可能性，并且可以与双接触孔工艺兼容。

公开(公告)号：US08969164B2

公开(公告)日：2015-03-03

申请号：US14002456

申请日：2012-03-23

申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08 ,  H01L21/84 ,  H01L27/12 ,  H01L21/8234 ,  H01L29/51

CPC分类号： H01L29/7842 ,  H01L21/823412 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0847 ,  H01L29/51 ,  H01L29/66431

摘要： A semiconductor structure comprises a substrate, a gate stack, a base area, and a source/drain region, wherein the gate stack is located on the base area, the source/drain region is located in the base area, and the base area is located on the substrate. A supporting isolated structure is provided between the base area and the substrate, wherein part of the supporting structure is connected to the substrate; a cavity is provided between the base area and the substrate, wherein the cavity is composed of the base area, the substrate and the supporting isolated structure. A stressed material layer is provided on both sides of the gate stack, the base area and the supporting isolated structure. Correspondingly, a method is provided for manufacturing such a semiconductor structure, which inhibits the short channel effect, reduces the parasitic capacitance and leakage current, and enhances the steepness of the source/drain region.

摘要翻译： 半导体结构包括衬底，栅极堆叠，基极区域和源极/漏极区域，其中栅极堆叠层位于基极区域上，源极/漏极区域位于基极区域中，并且基极区域是 位于基板上。 在基部区域和基板之间设置支撑隔离结构，其中支撑结构的一部分连接到基板; 在基部区域和基板之间设置空腔，其中空腔由基底区域，基底和支撑隔离结构构成。 在栅极堆叠的两侧，基部区域和支撑隔离结构上设置应力材料层。 相应地，提供了一种用于制造这种半导体结构的方法，其抑制短沟道效应，降低寄生电容和漏电流，并且增强源/漏区的陡度。

公开(公告)号：US08828840B2

公开(公告)日：2014-09-09

申请号：US13379546

申请日：2011-04-26

申请人： Zhijiong Luo ,  Huilong Zhu ,  Haizhou Yin

发明人： Zhijiong Luo ,  Huilong Zhu ,  Haizhou Yin

IPC分类号： H01L21/762 ,  H01L21/02

CPC分类号： H01L21/76232 ,  H01L21/02381 ,  H01L21/02521 ,  H01L21/02639 ,  H01L21/02647

摘要： A semiconductor device and a method for manufacturing the same are disclosed. The method comprises: forming at least one trench in a first semiconductor layer, wherein at least lower portions of respective sidewalls of the trench tilt toward outside of the trench; filling a dielectric material in the trench, thinning the first semiconductor layer so that the first semiconductor layer is recessed with respect to the dielectric material, and epitaxially growing a second semiconductor layer on the first semiconductor layer, wherein the first semiconductor layer and the semiconductor layer comprise different materials from each other. According to embodiments of the disclosure, defects occurring during the heteroepitaxial growth can be effectively suppressed.

摘要翻译： 公开了一种半导体器件及其制造方法。 该方法包括：在第一半导体层中形成至少一个沟槽，其中沟槽的各个侧壁的至少下部部分朝向沟槽的外侧倾斜; 在沟槽中填充介电材料，使第一半导体层变薄，使得第一半导体层相对于电介质材料凹陷，并且在第一半导体层上外延生长第二半导体层，其中第一半导体层和半导体层 包括彼此不同的材料。 根据本公开的实施例，可以有效地抑制在异质外延生长期间发生的缺陷。

公开(公告)号：US08766371B2

公开(公告)日：2014-07-01

申请号：US13256866

申请日：2011-02-25

申请人： Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Qingqing Liang ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L21/70

CPC分类号： H01L29/4983 ,  H01L21/823807 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/66545 ,  H01L29/7845

摘要： There is provided a semiconductor structure and a method for manufacturing the same. The semiconductor structure according to the present invention comprises: a semiconductor substrate; a channel region formed on the semiconductor substrate; a gate stack formed on the channel region; and source/drain regions formed on both sides of the channel region and embedded in the semiconductor substrate. The gate stack comprises: a gate dielectric layer formed on the channel region; and a conductive layer positioned on the gate dielectric layer. For an nMOSFET, the conductive layer has a compressive stress to apply a tensile stress to the channel region; and for a pMOSFET, the conductive layer has a tensile stress to apply a compressive stress to the channel region.

摘要翻译： 提供半导体结构及其制造方法。 根据本发明的半导体结构包括：半导体衬底; 形成在半导体衬底上的沟道区; 形成在沟道区上的栅叠层; 以及形成在沟道区两侧并嵌入在半导体衬底中的源/漏区。 栅极堆叠包括：形成在沟道区上的栅极电介质层; 以及位于栅介质层上的导电层。 对于nMOSFET，导电层具有将压应力施加到沟道区的压应力; 并且对于pMOSFET，导电层具有拉伸应力以向沟道区域施加压应力。

公开(公告)号：US08754503B2

公开(公告)日：2014-06-17

申请号：US13355946

申请日：2012-01-23

申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L23/52 ,  H01L21/768

CPC分类号： H01L27/1218

摘要： The present invention provides a strip plate structure and a method for manufacturing the same. The strip plate structure comprises a strip plate array, which comprises a plurality of strip plates arranged with spacing in a predetermined direction on a same plane, wherein each of the strip plates has a first surface and a second surface opposite to the first surface and the strip plate array is arranged on a plane parallel to the first surface of the strip plates; a plurality of strip sheets which connect neighboring ones of the strip plates; flexible material layers, which are located on at least a portion of the surfaces of the strip sheets and/or on at least a portion of the surfaces of the strip plates.

摘要翻译： 本发明提供一种带状板结构及其制造方法。 带状板结构包括条板阵列，其包括在同一平面上以预定方向间隔布置的多个带状板，其中每个带状板具有第一表面和与第一表面相对的第二表面， 带板阵列布置在平行于带状板的第一表面的平面上; 多个带状片，其连接相邻的条板; 柔性材料层位于带状片的至少一部分表面上和/或在带状板的至少一部分表面上。

公开(公告)号：US08674449B2

公开(公告)日：2014-03-18

申请号：US13576550

申请日：2011-11-25

申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L21/70 ,  H01L27/088

CPC分类号： H01L29/785 ,  H01L27/0924 ,  H01L29/66795

摘要： A semiconductor device and a method for manufacturing the same are disclosed. In one embodiment, the semiconductor device may comprise a semiconductor layer, a fin formed by patterning the semiconductor layer, and a gate stack crossing over the fin. The fin may comprise a doped block region at the bottom portion thereof. According to the embodiment, it is possible to effectively suppress current leakage at the bottom portion of the fin by the block region.

摘要翻译： 公开了一种半导体器件及其制造方法。 在一个实施例中，半导体器件可以包括半导体层，通过图案化半导体层形成的鳍和跨在翅片上的栅极堆叠。 鳍可以在其底部包括掺杂块区域。 根据本实施方式，能够通过块区域有效地抑制翅片底部的电流泄漏。

公开(公告)号：US08643061B2

公开(公告)日：2014-02-04

申请号：US12908024

申请日：2010-10-20

申请人： Haizhou Yin ,  Dae-Gyu Park ,  Oleg Gluschenkov ,  Zhijiong Luo ,  Dominic Schepis ,  Jun Yuan

发明人： Haizhou Yin ,  Dae-Gyu Park ,  Oleg Gluschenkov ,  Zhijiong Luo ,  Dominic Schepis ,  Jun Yuan

IPC分类号： H01L29/66

CPC分类号： H01L21/84 ,  H01L21/76254 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/1203 ,  H01L29/1054 ,  H01L29/66651 ,  H01L29/78

摘要： A semiconductor structure is provided. The structure includes an n-type field-effect-transistor (NFET) being formed directly on top of a strained silicon layer, and a p-type field-effect-transistor (PFET) being formed on top of the same stained silicon layer but via a layer of silicon-germanium (SiGe). The strained silicon layer may be formed on top of a layer of insulating material or a silicon-germanium layer with graded Ge content variation. Furthermore, the NFET and PFET are formed next to each other and are separated by a shallow trench isolation (STI) formed inside the strained silicon layer. Methods of forming the semiconductor structure are also provided.

摘要翻译： 提供半导体结构。 该结构包括直接形成在应变硅层的顶部上的n型场效应晶体管（NFET），以及形成在同一染色硅层顶部的p型场效应晶体管（PFET），但是 通过一层硅 - 锗（SiGe）。 应变硅层可以形成在具有分级Ge含量变化的绝缘材料层或硅 - 锗层的顶部上。 此外，NFET和PFET彼此相邻形成，并且通过形成在应变硅层内部的浅沟槽隔离（STI）分开。 还提供了形成半导体结构的方法。

公开(公告)号：US08598666B2

公开(公告)日：2013-12-03

申请号：US13504935

申请日：2011-11-03

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L27/12

CPC分类号： H01L27/124 ,  H01L21/743 ,  H01L27/1218 ,  H01L29/78

摘要： The present invention relates to a semiconductor structure and a method for manufacturing the same. A semiconductor structure comprises: a semiconductor substrate; a first insulating material layer, a first conductive material layer, a second insulating material layer, a second conductive material layer and an insulating buried layer formed in sequence on the semiconductor substrate; a semiconductor layer bonded on the insulating buried layer; transistors formed on the semiconductor layer, the channel regions of the transistors each being formed in the semiconductor layer and each having a back-gate formed from the second conductive material layer; a dielectric layer covering the semiconductor layer and the transistors; isolation structures for at least electrically isolating each transistor from its adjacent transistors, the top of the isolation structures being flush with or slightly higher than the upper surface of the semiconductor layer, and the bottom of the isolation structures being in the second insulating material layer; and a conductive contact running through the dielectric layer and extending down into the first conductive material layer.

摘要翻译： 半导体结构及其制造方法技术领域本发明涉及半导体结构及其制造方法。 半导体结构包括：半导体衬底; 在半导体衬底上依次形成第一绝缘材料层，第一导电材料层，第二绝缘材料层，第二导电材料层和绝缘掩埋层; 接合在绝缘掩埋层上的半导体层; 形成在半导体层上的晶体管，晶体管的沟道区各自形成在半导体层中，每一个具有由第二导电材料层形成的背栅; 覆盖半导体层和晶体管的电介质层; 用于至少将每​​个晶体管与其相邻晶体管电隔离的隔离结构，隔离结构的顶部与半导体层的上表面齐平或略高，隔离结构的底部位于第二绝缘材料层中; 以及导电接触件，其穿过介电层并向下延伸到第一导电材料层中。

公开(公告)号：US08546910B2

公开(公告)日：2013-10-01

申请号：US13380723

申请日：2011-08-24

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L21/70

CPC分类号： H01L29/66772 ,  H01L29/78603 ,  H01L29/78696

摘要： The present invention provides a semiconductor structure, which comprises a substrate, a semiconductor base, a cavity, a gate stack, sidewall spacers, source/drain regions and a contact layer; wherein, the gate stack is located on the semiconductor base, the sidewall spacers are located on sidewalls of the gate stack, the source/drain regions are embedded within the semiconductor base and located on both sides of the gate stack, the cavity is embedded within the substrate, and the semiconductor base is suspended over the cavity, the thickness in the middle portion of the semiconductor base is greater than the thicknesses at both ends of the semiconductor base in a direction along the gate length, and both ends of the semiconductor base are connected with the substrate in a direction along the gate width; the contact layer covers exposed surfaces of the source/drain regions. Accordingly, the present invention further provides a method for manufacturing a semiconductor structure, which is favorable for reducing the contact resistance at the source/drain regions, enhancing the device performance, lowering the cost and simplifying the manufacturing process.

摘要翻译： 本发明提供一种半导体结构，其包括衬底，半导体基底，空腔，栅极堆叠，侧壁间隔物，源极/漏极区域和接触层; 其中，所述栅极堆叠位于所述半导体基底上，所述侧壁间隔物位于所述栅极堆叠的侧壁上，所述源极/漏极区域被嵌入所述半导体基底内并且位于所述栅极堆叠的两侧，所述腔体嵌入 衬底和半导体衬底悬挂在空腔上，半导体衬底的中间部分的厚度大于沿着栅极长度方向的半导体衬底的两端的厚度，并且半导体衬底的两端 沿着所述栅极宽度的方向与所述基板连接; 接触层覆盖源极/漏极区域的暴露表面。 因此，本发明还提供了一种制造半导体结构的方法，其有利于降低源/漏区的接触电阻，提高器件性能，降低成本并简化制造工艺。