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    TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN
    81.
    发明申请
    TRANSISTOR WITH RECESSED CHANNEL AND RAISED SOURCE/DRAIN 审中-公开
    带有通道和放大源/漏极的晶体管

    公开(公告)号：US20130175579A1

    公开(公告)日：2013-07-11

    申请号：US13347161

    申请日：2012-01-10

    申请人： Kangguo Cheng ,  Ali Khakifirooz ,  Sivananda Kanakasabapathy ,  Pranita Kulkarni ,  Balasubramanian S. Haran

    发明人： Kangguo Cheng ,  Ali Khakifirooz ,  Sivananda Kanakasabapathy ,  Pranita Kulkarni ,  Balasubramanian S. Haran

    IPC分类号： H01L29/78 ,  H01L21/335

    CPC分类号： H01L29/66795 ,  H01L29/66545 ,  H01L29/7848 ,  H01L29/785

    摘要： A transistor includes a first semiconductor layer. A second semiconductor layer is located on the first semiconductor layer. A portion of the second semiconductor layer is removed to expose a first portion of the first semiconductor layer and to provide vertical sidewalls of the second semiconductor layer. A gate spacer is located on the second semiconductor layer. A gate dielectric includes a first portion located on the first portion of the first semiconductor layer and a second portion adjacent to the vertical sidewalls of the second semiconductor layer. A gate conductor is located on the first portion of the gate dielectric and abuts the gate dielectric second portion. A channel region is located in at least part of the first portion of the first semiconductor layer. Raised source/drain regions are located in the second semiconductor layer. At least part of the raised source/drain regions is located below the gate spacer.

    摘要翻译： 晶体管包括第一半导体层。 第二半导体层位于第一半导体层上。 去除第二半导体层的一部分以暴露第一半导体层的第一部分并提供第二半导体层的垂直侧壁。 栅极间隔物位于第二半导体层上。 栅极电介质包括位于第一半导体层的第一部分上的第一部分和与第二半导体层的垂直侧壁相邻的第二部分。 栅极导体位于栅极电介质的第一部分上并邻接栅极电介质第二部分。 沟道区位于第一半导体层的第一部分的至少一部分中。 上升的源极/漏极区域位于第二半导体层中。 凸起的源极/漏极区域的至少一部分位于栅极间隔物的下方。

    Replacement Gate ETSOI with Sharp Junction
    82.
    发明申请
    Replacement Gate ETSOI with Sharp Junction 审中-公开
    更换门ETSOI与夏普结

    公开(公告)号：US20130032876A1

    公开(公告)日：2013-02-07

    申请号：US13195153

    申请日：2011-08-01

    申请人： Kangguo CHENG ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

    发明人： Kangguo CHENG ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

    IPC分类号： H01L27/088 ,  H01L21/336 ,  H01L29/78

    CPC分类号： H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66795

    摘要： A transistor structure includes a channel disposed between a source and a drain; a gate conductor disposed over the channel and between the source and the drain; and a gate dielectric layer disposed between the gate conductor and the source, the drain and the channel. In the transistor structure a lower portion of the source and a lower portion of the drain that are adjacent to the channel are disposed beneath and in contact with the gate dielectric layer to define a sharply defined source-drain extension region. Also disclosed is a replacement gate method to fabricate the transistor structure.

    摘要翻译： 晶体管结构包括设置在源极和漏极之间的沟道; 设置在所述通道上并且在所述源极和所述漏极之间的栅极导体; 以及设置在栅极导体和源极之间的栅介质层，漏极和沟道。 在晶体管结构中，源极的下部和与沟道相邻的漏极的下部设置在栅极介电层的下方并与栅极介电层接触以限定明确限定的源 - 漏扩展区。 还公开了制造晶体管结构的替代栅极方法。

    Replacement gate ETSOI with sharp junction
    84.
    发明授权
    Replacement gate ETSOI with sharp junction 有权
    替换门ETSOI与尖端连接

    公开(公告)号：US08673708B2

    公开(公告)日：2014-03-18

    申请号：US13611044

    申请日：2012-09-12

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

    IPC分类号： H01L21/338

    CPC分类号： H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66795

    摘要： A method includes providing a silicon-on-insulator wafer (e.g., an ETSOI wafer); forming a sacrificial gate structure that overlies a sacrificial insulator layer; forming raised source/drains adjacent to the sacrificial gate structure; depositing a layer that covers the raised source/drains and that surrounds the sacrificial gate structure; and removing the sacrificial gate structure leaving an opening that extends to the sacrificial insulator layer. The method further includes widening the opening so as to expose some of the raised source/drains, removing the sacrificial insulator layer and forming a spacer layer on sidewalls of the opening, the spacer layer covering only an upper portion of the exposed raised source/drains, and depositing a layer of gate dielectric material within the opening. A gate conductor is deposited within the opening.

    摘要翻译： 一种方法包括提供绝缘体上硅晶片（例如，ETSOI晶片）; 形成覆盖牺牲绝缘体层的牺牲栅极结构; 形成与牺牲栅极结构相邻的凸起的源极/漏极; 沉积覆盖升高的源极/漏极并围绕牺牲栅极结构的层; 以及去除牺牲栅极结构，留下延伸到牺牲绝缘体层的开口。 该方法还包括加宽开口以暴露一些升高的源极/漏极，去除牺牲绝缘体层并在开口的侧壁上形成间隔层，间隔层仅覆盖暴露的升高的源极/漏极的上部 ，并且在开口内沉积一层栅介质材料。 栅极导体沉积在开口内。

    REPLACEMENT GATE ETSOI WITH SHARP JUNCTION
    85.
    发明申请
    REPLACEMENT GATE ETSOI WITH SHARP JUNCTION 有权
    用快速接头更换门ETSOI

    公开(公告)号：US20130034938A1

    公开(公告)日：2013-02-07

    申请号：US13611044

    申请日：2012-09-12

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Ali Khakifirooz

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66545 ,  H01L29/66628 ,  H01L29/66772 ,  H01L29/66795

    摘要： A method includes providing a silicon-on-insulator wafer (e.g., an ETSOI wafer); forming a sacrificial gate structure that overlies a sacrificial insulator layer; forming raised source/drains adjacent to the sacrificial gate structure; depositing a layer that covers the raised source/drains and that surrounds the sacrificial gate structure; and removing the sacrificial gate structure leaving an opening that extends to the sacrificial insulator layer. The method further includes widening the opening so as to expose some of the raised source/drains, removing the sacrificial insulator layer and forming a spacer layer on sidewalls of the opening, the spacer layer covering only an upper portion of the exposed raised source/drains, and depositing a layer of gate dielectric material within the opening. A gate conductor is deposited within the opening.

    摘要翻译： 一种方法包括提供绝缘体上硅晶片（例如，ETSOI晶片）; 形成覆盖牺牲绝缘体层的牺牲栅极结构; 形成与牺牲栅极结构相邻的凸起的源极/漏极; 沉积覆盖升高的源极/漏极并围绕牺牲栅极结构的层; 以及去除牺牲栅极结构，留下延伸到牺牲绝缘体层的开口。 该方法还包括加宽开口以暴露一些升高的源极/漏极，去除牺牲绝缘体层并在开口的侧壁上形成间隔层，间隔层仅覆盖暴露的升高的源极/漏极的上部 ，并且在开口内沉积一层栅介质材料。 栅极导体沉积在开口内。

    Junctionless transistor
    90.
    发明授权
    Junctionless transistor 有权
    无结晶体晶体管

    公开(公告)号：US08803233B2

    公开(公告)日：2014-08-12

    申请号：US13242861

    申请日：2011-09-23

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tak H. Ning

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tak H. Ning

    IPC分类号： H01L29/778

    CPC分类号： H01L21/823807 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/78654 ,  H01L29/78696

    摘要： A transistor includes a semiconductor layer, and a gate dielectric is formed on the semiconductor layer. A gate conductor is formed on the gate dielectric and an active area is located in the semiconductor layer underneath the gate dielectric. The active area includes a graded dopant region that has a higher doping concentration near a top surface of the semiconductor layer and a lower doping concentration near a bottom surface of the semiconductor layer. This graded dopant region has a gradual decrease in the doping concentration. The transistor also includes source and drain regions that are adjacent to the active region. The source and drain regions and the active area have the same conductivity type.

    摘要翻译： 晶体管包括半导体层，并且在半导体层上形成栅极电介质。 栅极导体形成在栅极电介质上，并且有源区位于栅极电介质下方的半导体层中。 有源区包括在半导体层的顶表面附近具有较高掺杂浓度的渐变掺杂区和在半导体层的底表面附近的较低的掺杂浓度。 该渐变掺杂剂区域的掺杂浓度逐渐降低。 晶体管还包括与有源区相邻的源区和漏区。 源极和漏极区域和有源区域具有相同的导电类型。