公开(公告)号：US20060062045A1

公开(公告)日：2006-03-23

申请号：US11206995

申请日：2005-08-19

Applicant: Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

Inventor： Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

IPC: G11C16/04

CPC classification number: G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5621 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.

公开(公告)号：US06683812B2

公开(公告)日：2004-01-27

申请号：US10304046

申请日：2002-11-26

Applicant: Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

Inventor： Kunihiro Katayama ,  Takayuki Tamura ,  Kiyoshi Inoue

IPC: G11C700

CPC classification number: G11C16/28 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/30 ,  G11C2211/5621 ,  G11C2211/5632 ,  G11C2211/5634 ,  G11C2211/5641 ,  G11C2211/5642

Abstract: A semiconductor memory includes a memory block consisting of a plurality of cells, a write control section, and a read control section. The write control section sets a potential to each of the plurality of cells in such a manner that the potential corresponds to a level indicated by a bit data string obtained by arranging pieces of bit data which are stored in buffers A and B and which are to be stored in the cell in the order of the buffer A and the buffer B. The read control section has a discriminator corresponding to each of the plurality of cells. The discriminator sets a threshold voltage to a potential level that corresponds to a number of discriminating operations to be performed with respect to a corresponding cell and a result of a discriminating operation already performed with respect to the cell. As a result of these operations, the semiconductor memory can determine the pieces of bit data in the order of the buffer A and the buffer B every time the discriminating operation is performed with respect to the cell.

公开(公告)号：US06508889B2

公开(公告)日：2003-01-21

申请号：US09826826

申请日：2001-04-06

Applicant: Akihiro Kikuchi ,  Yasuo Iijima ,  Kiyoshi Inoue

Inventor： Akihiro Kikuchi ,  Yasuo Iijima ,  Kiyoshi Inoue

IPC: H01B1200

CPC classification number: B21C37/04 ,  B32B15/017 ,  C22C27/02 ,  C22F1/18 ,  H01L39/2409 ,  Y10S420/901 ,  Y10S505/806 ,  Y10S505/815 ,  Y10T29/49014

Abstract: A high-performance Nb3Al extra-fine multifilamentary superconducting wire is produced simply and inexpensively through the improvement of critical values, Tc, Hc2 and Jc, without the addition of third elements such as Ge, Si and Cu. A first rapid heating and quenching treatment is applied to an Nb/Al composite wire having an atomic ratio of Al to Nb from 1:2.5 to 1:3.5 and having an extra-fine multifilamentary structure to form a BCC alloy phase comprising Nb with Al supersaturatedly dissolved therein wherein the treatment comprises heating the composite wire up to a temperature not lower than 1900° C. within two seconds and then introducing it into a molten metal at a temperature not higher than 400° C. to rapidly quench it. The wire is subjected to a second rapid heating and quenching treatment to form an A15-Nb3Al compound having a low degree of crystalline order but having an approximately stoichiometric composition wherein the second treatment comprises heating the wire up to a temperature not lower than 1500° C. within two seconds and then introducing it into a molten metal at a temperature not higher than 400° C. Then, an additional heat treatment is conducted to improve the degree of crystalline order of the Al5-Nb3Al compound having an approximately stoichiometric composition.

Abstract translation: 通过提高临界值Tc，Hc2和Jc，不需要添加诸如Ge，Si和Cu的第三元素，简单且廉价地制造高性能Nb3Al超细多丝超导线。 对原子比为Al:Nb的Nb / Al复合线进行第一快速加热淬火处理，其比例为1:2.5〜1:3.5，并且具有超细多丝结构，以形成含有Nb的BCC合金相，Al 过饱和溶解在其中，其中处理包括在两秒钟内将复合线材加热至不低于1900℃的温度，然后在不高于400℃的温度下将其引入熔融金属中以快速淬火。 对线材进行第二次快速加热淬火处理以形成具有低结晶度但具有近似化学计量组成的A15-Nb3Al化合物，其中第二处理包括将线材加热至不低于1500℃的温度 然后在不高于400℃的温度下将其引入熔融金属中，然后进行额外的热处理，以提高具有大致化学计量组成的Al5-Nb3Al化合物的结晶度。

公开(公告)号：US06388920B2

公开(公告)日：2002-05-14

申请号：US09886133

申请日：2001-06-22

Applicant: Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

Inventor： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

IPC: G11C1606

CPC classification number: G11C16/349 ,  G11C29/76 ,  G11C29/88

Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

公开(公告)号：US06317371B2

公开(公告)日：2001-11-13

申请号：US09824778

申请日：2001-04-04

Applicant: Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

Inventor： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

IPC: G11C700

CPC classification number: G11C16/349 ,  G11C29/76 ,  G11C29/88

Abstract: In response to a read command received by a system interface unit for accessing a plurality of blocks of data stored in said non-volatile semiconductor memory, a controller carries out selective read operations of blocks of data to two memories from the non-volatile semiconductor memory. The controller also carries out parallel operations of data transferring a first block of data, which has already been subjected to error detection and error correction operations by an error correction unit, from one of the two memories to a host system via said system interface unit and of data transferring of a second block of data to be subjected to the error detection and error correction operation, from said non-volatile semiconductor memory to the other of the two memories.

Abstract translation: 响应于由用于访问存储在所述非易失性半导体存储器中的多个数据块的系统接口单元接收到的读取命令，控制器对来自非易失性半导体存储器的两个存储器执行数据块的选择性读取操作 。 所述控制器还执行数据的并行操作，所述数据传输已经经过错误校正单元的错误检测和纠错操作的第一数据块经由所述系统接口单元从所述两个存储器之一传送到主机系统，并且 将要进行错误检测和纠错操作的第二数据块的数据传输从所述非易失性半导体存储器传输到两个存储器中的另一个。

公开(公告)号：US06236601B1

公开(公告)日：2001-05-22

申请号：US09477665

申请日：2000-01-05

Applicant: Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

Inventor： Kunihiro Katayama ,  Takayuki Tamura ,  Satoshi Watatani ,  Kiyoshi Inoue ,  Shigemasa Shiota ,  Masashi Naito

IPC: G11C700

CPC classification number: G11C16/349 ,  G11C29/76 ,  G11C29/88

Abstract: A semiconductor memory device having an electrically erasable nonvolatile memory, wherein the nonvolatile memory has management information regions for individual blocks and fault registration regions for registering fault addresses. If a block is accessed and found to be faulty, the fault registration is performed so that a partially faulty memory can be used without an increase in access time. By registering the management information address for executing the interchanges of blocks in one-to-one correspondence in the administrative information region, moreover, the blocks can be interchanged depending upon the frequency of rewriting.

Abstract translation: 一种具有电可擦除非易失性存储器的半导体存储器件，其中非易失性存储器具有用于各个块的管理信息区域和用于登记故障地址的故障登记区域。 如果一个块被访问并发现有故障，则执行故障登记，以便可以使用部分故障的存储器而不增加访问时间。 此外，通过在管理信息区域中一一对应地登记用于执行块的交换的管理信息地址，并且可以根据重写的频率来交换块。

公开(公告)号：US5671382A

公开(公告)日：1997-09-23

申请号：US915204

申请日：1992-04-20

Applicant: Yooichi Shintani ,  Kazunori Kuriyama ,  Tohru Shonai ,  Eiki Kamada ,  Kiyoshi Inoue

Inventor： Yooichi Shintani ,  Kazunori Kuriyama ,  Tohru Shonai ,  Eiki Kamada ,  Kiyoshi Inoue

IPC: G06F9/38

CPC classification number: G06F9/3889 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3861 ,  G06F9/3885

Abstract: An information processing apparatus in which instructions are processed one by one conceptually and results thereof are conceptually orderly written into a memory comprises an instruction control circuit capable of decoding M instructions and reading operands in parallel, N (N.gtoreq.M) execution circuits capable of executing a plurality of instructions mutually in parallel, a detection circuit for determining whether all of M execution circuits of the N execution circuits required by the M instructions decoded by the instruction control circuit are vacant or not, and a reserve circuit for reserving the execution of the M decoded instruction while the detection fails to detect sufficient vacancy.

Abstract translation: 一种信息处理设备，其中概念地逐个处理指令，并且其结果在概念上有序地写入存储器包括能够并行地解码M个指令和读取操作数的指令控制电路，N（N> / = M）个执行电路能够 执行并行执行多个指令的检测电路，用于确定由指令控制电路解码的M个指令所需的N个执行电路的所有M个执行电路是否为空的检测电路，以及用于保留执行的备用电路 的M解码指令，而检测不能检测到足够的空位。

公开(公告)号：US5567342A

公开(公告)日：1996-10-22

申请号：US458438

申请日：1995-06-02

Applicant: Kiyoshi Inoue ,  Masakuni Hirata

Inventor： Kiyoshi Inoue ,  Masakuni Hirata

IPC: C10M163/00 ,  C10M141/10 ,  C10N10/02 ,  C10N10/04 ,  C10N30/04 ,  C10N30/10 ,  C10N40/25 ,  F02B77/04 ,  C10M137/06 ,  C10M133/56

CPC classification number: C10M141/10 ,  C10M2205/026 ,  C10M2205/04 ,  C10M2207/023 ,  C10M2207/024 ,  C10M2207/026 ,  C10M2207/027 ,  C10M2207/028 ,  C10M2207/123 ,  C10M2207/129 ,  C10M2207/22 ,  C10M2207/262 ,  C10M2207/282 ,  C10M2207/288 ,  C10M2207/34 ,  C10M2209/084 ,  C10M2215/06 ,  C10M2215/064 ,  C10M2215/065 ,  C10M2215/066 ,  C10M2215/067 ,  C10M2215/068 ,  C10M2215/22 ,  C10M2215/221 ,  C10M2215/225 ,  C10M2215/226 ,  C10M2215/28 ,  C10M2215/30 ,  C10M2219/046 ,  C10M2219/087 ,  C10M2219/088 ,  C10M2219/089 ,  C10M2223/041 ,  C10M2223/045 ,  C10N2210/02 ,  C10N2240/10 ,  C10N2240/101 ,  C10N2240/102 ,  C10N2240/103 ,  C10N2240/104 ,  C10N2240/105 ,  C10N2240/106 ,  F02B77/04

Abstract: An internal combustion engine lubricating oil composition adapted for used with a maintenance-free system of engine and having excellent properties including oxidation stability, resistance against sludge formation and ability to clean the engine. The composition is characterized in that it comprises ingredients (A) through (D) below as essential components on the basis of total amount of composition and the total base number of the composition is between 2.0 and 6.0 mgKOH/g: (A) a specific alkaline earth metal type cleaning agent, (B) zinc dialkyldithiophosphate expressed by a specific general formula (1), (C) a succinic acid imide type ashless dispersant and (D) a phenol type and/or amine type ashless antioxidant.

Abstract translation: 一种内燃机润滑油组合物，适用于发动机免维护系统，具有优异的性能，包括氧化稳定性，抗污泥形成能力和清洁发动机的能力。 该组合物的特征在于，以组合物总量为基础，将下述成分（A）〜（D）作为必要成分，组合物的总碱值为2.0〜6.0mgKOH / g：（A） 碱土金属型清洗剂，（B）由特定通式（1）表示的二烷基二硫代磷酸锌，（C）琥珀酸酰亚胺型无灰分散剂和（D）酚型和/或胺型无灰抗氧化剂。

公开(公告)号：US5534087A

公开(公告)日：1996-07-09

申请号：US121379

申请日：1993-09-15

Applicant: Tooru Hirota ,  Akira Imai ,  Tomoyuki Kumano ,  Masamitsu Ichihara ,  Yoshikazu Sakai ,  Kiyoshi Inoue ,  Hiroshi Maeda

Inventor： Tooru Hirota ,  Akira Imai ,  Tomoyuki Kumano ,  Masamitsu Ichihara ,  Yoshikazu Sakai ,  Kiyoshi Inoue ,  Hiroshi Maeda

IPC: C22C9/00 ,  C22F1/08

CPC classification number: C22C9/00 ,  C22F1/08

Abstract: A method for producing a Cu--Ag alloy based conductive material containing about 10% to about 20% at % Ag, that involves the steps of continuously casting the alloy into a rod followed by quickly cooling the rod, cold-working the rod to a reduction in area of 80% or more, then heat treating the cold-worked rod at a temperature of 250.degree. C. to 350.degree. C. for 1 hour or more to form a heat-treated rod, and thereafter cold-working the heat-treated rod to a reduction in area of 90% or more as defined based on the cast rod to produce conductive material having a high strength of 700 MPa or more and conductivity of 75% IACA or more.

Abstract translation: 一种制备含有约10％至约20％at％Ag的Cu-Ag合金基导电材料的方法，其包括将合金连续铸入棒中的步骤，然后快速冷却棒，将棒冷却至 面积减少80％以上，然后在250〜350℃的温度下对冷加工棒进行1小时以上的热处理，形成热处理棒，然后冷热 根据铸棒测定的面积减小到90％以上的面积，制成具有700MPa以上的高强度和75％IACA以上的导电性的导电材料。

公开(公告)号：US5528535A

公开(公告)日：1996-06-18

申请号：US399511

申请日：1995-03-07

Applicant: Shigeru Honjo ,  Kazumasa Yanagisawa ,  Kiyoshi Inoue

Inventor： Shigeru Honjo ,  Kazumasa Yanagisawa ,  Kiyoshi Inoue

IPC: G11C14/00 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  G11C11/406

CPC classification number: G11C11/22

Abstract: A memory matrix--which comprises memory cells arranged in matrix, each made up of a ferroelectric capacitor and an address selection MOSFET--is divided for each word line into a plurality of memory blocks. Each of the memory blocks is provided with a mode storage circuit that stores a DRAM mode (volatile mode) or NV mode (non-volatile mode) in one-to-one correspondence for each memory block, and with a refresh operation count circuit that counts for each memory block the number of times the refresh operations is performed consecutively. During an n-th refresh operation (where n is a predetermined number of times), a memory access is made to temporarily change the plate voltage of the ferroelectric capacitor from one voltage to another and at the same time the mode storage circuit is changed from the DRAM mode to the NV mode. When a read or write operation to and from a memory cell in the memory block is performed, the mode storage circuit is changed from the NV mode to the DRAM mode. The refresh operation is omitted for the memory block that was set to the NV mode according to the stored information in the mode storage circuit.

Abstract translation: 存储矩阵，其包括以矩阵排列的每个由铁电电容器和地址选择MOSFET构成的存储单元，其被划分为多个存储块。 每个存储块设置有模式存储电路，其针对每个存储块以一对应的对应关系存储DRAM模式（易失性模式）或NV模式（非易失性模式），并且利用刷新操作计数电路 对每个内存块进行连续执行刷新操作的次数。 在第n次刷新操作（其中n是预定次数）的情况下，进行存储器访问以将铁电电容器的板电压从一个电压临时地改变为另一个电压，同时模式存储电路从 DRAM模式为NV模式。 当执行对存储器块中的存储单元的读取或写入操作时，模式存储电路从NV模式改变为DRAM模式。 根据模式存储电路中存储的信息，对于被设置为NV模式的存储器块，省略刷新操作。