Capacitive fluid sensor
    81.
    发明授权
    Capacitive fluid sensor 失效
    电容式液体传感器

    公开(公告)号:US4939468A

    公开(公告)日:1990-07-03

    申请号:US302881

    申请日:1989-01-30

    Inventor: Kiyoshi Takeuchi

    CPC classification number: G01N27/24

    Abstract: To increase the sealing effect with increasing fluid pressure in a capacitive fluid sensor for sensing a dielectric constant of fluid, the sensor comprises a sensor housing, a fluid outlet pipe connected midway in the sensor housing, an internal electrode, a first cylindrical insulating internal electrode support member disposed within the sensor housing between the fluid outlet pipe and a sensor housing end, and a sealing member disposed between the first cylindrical support member and sensor housing end. It is preferable to dispose a second flat insulating internal electrode support member formed with a central annular portion and plural arms extending from the annular portion so as to be fitted to a swollen-out portion of the sensor housing to reduce fluid resistance.

    Abstract translation: 为了增加用于感测流体介电常数的电容式流体传感器中增加流体压力的密封效果,传感器包括传感器壳体,连接在传感器壳体中途的流体出口管,内部电极,第一圆柱形绝缘内部电极 支撑构件设置在传感器壳体内的流体出口管和传感器外壳端之间,密封构件设置在第一圆柱形支撑构件和传感器外壳端之间。 优选地,设置形成有中心环状部分和从环形部分延伸的多个臂的第二平坦绝缘内部电极支撑构件,以便配合到传感器壳体的膨胀部分以减小流体阻力。

    Information storage device and test method of setting a test condition for information storage device outside range of presupposed real use conditions
    85.
    发明授权
    Information storage device and test method of setting a test condition for information storage device outside range of presupposed real use conditions 有权
    信息存储装置和设置信息存储装置的测试条件在预先设定的实际使用条件范围之外的试验方法

    公开(公告)号:US08984353B2

    公开(公告)日:2015-03-17

    申请号:US13010363

    申请日:2011-01-20

    Inventor: Kiyoshi Takeuchi

    Abstract: A method of testing the operational margin of an information storage device having marked random variations, and an information storage device having the function of self-diagnosing the operational margin, are provided. The test method includes testing an information storage device including a plurality of memory bits as the test condition is set so as to be outside a range of conditions that may be presupposed in real use of the information storage device and of counting the number of memory bits that fail in operation. The test method also includes verifying the size of the operational margin of the information storage device based on the count value. The test condition is made severe and the reference value is set to a fairly large value to enable the operational margin against the noise to be tested highly accurately.

    Abstract translation: 提供一种测试具有标记的随机变化的信息存储设备的操作余量的方法,以及具有自诊断操作余量功能的信息存储设备。 测试方法包括测试包括多个存储器位的信息存储设备,因为测试条件被设置为处于实际使用信息存储设备预先设定的条件的范围内,并且对存储器位数进行计数 失败了。 测试方法还包括基于计数值验证信息存储设备的操作余量的大小。 测试条件变得严重,参考值被设置为相当大的值,以使得能够高精度地测试噪声的操作余量。

    Double rack and pinion oscillating device
    86.
    发明授权
    Double rack and pinion oscillating device 有权
    双齿轮和小齿轮摆动装置

    公开(公告)号:US08646376B2

    公开(公告)日:2014-02-11

    申请号:US12553376

    申请日:2009-09-03

    CPC classification number: F15B15/065 F15B15/1433 F15B15/149

    Abstract: A plurality of ring-shaped sealing members are spaced from each other on the outer periphery of each of first and second end caps that seal openings of first and second cylinder holes. Ring-shaped flow paths are formed between adjacent ring-shaped sealing members. Parts of air flow paths that supply and discharge compressed air to and from pressure chambers of the cylinder holes are formed by the ring-shaped flow paths.

    Abstract translation: 多个环形密封构件在第一和第二端盖的每个的外周上彼此间隔开,从而密封第一和第二气缸孔的开口。 在相邻的环形密封件之间形成环形流路。 通过环形流路形成向气缸孔的压力室供给和排出压缩空气的空气流路的一部分。

    Semiconductor device and method for manufacturing the same
    87.
    发明授权
    Semiconductor device and method for manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号:US08581333B2

    公开(公告)日:2013-11-12

    申请号:US12922316

    申请日:2009-03-27

    Inventor: Kiyoshi Takeuchi

    Abstract: A first local wiring includes a convex portion protruding from a base and a protrusion protruding from a side surface of the convex portion. The convex portion of the first local wiring is connected to a lower conductive region of a first transistor while the protrusion is connected to a gate electrode of a second transistor. Moreover, the lower surface of the protrusion of the first local wiring is arranged at a height equal to or lower than the upper surface of the gate electrode of the second transistor.

    Abstract translation: 第一局部布线包括从基部突出的凸部和从凸部的侧面突出的突起。 第一局部布线的凸部连接到第一晶体管的下导电区域,同时突起连接到第二晶体管的栅电极。 此外,第一局部布线的突起的下表面布置在等于或低于第二晶体管的栅电极的上表面的高度。

    SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, AND METHODS OF MANUFACTURING THE SAME
    88.
    发明申请
    SEMICONDUCTOR DEVICE, SEMICONDUCTOR WAFER, AND METHODS OF MANUFACTURING THE SAME 审中-公开
    半导体器件,半导体器件及其制造方法

    公开(公告)号:US20120313172A1

    公开(公告)日:2012-12-13

    申请号:US13489128

    申请日:2012-06-05

    Abstract: This invention is to provide a semiconductor device having a reduced variation in the transistor characteristics. The semiconductor device has a SOI substrate, a first element isolation insulating layer, first and second conductivity type transistors, and first and second back gate contacts. The SOI substrate has a semiconductor substrate having first and second conductivity type layers, an insulating layer, and a semiconductor layer. The first element isolation insulating layer is buried in the SOI substrate, has a lower end reaching the first conductivity type layer, and isolates a first element region from a second element region. The first and second conductivity type transistors are located in the first and second element regions, respectively, and have respective channel regions formed in the semiconductor layer. The first and second back gate contacts are coupled to the second conductivity type layers in the first and second element regions, respectively.

    Abstract translation: 本发明提供一种具有减小的晶体管特性变化的半导体器件。 半导体器件具有SOI衬底,第一元件隔离绝缘层,第一和第二导电型晶体管以及第一和第二后栅极触点。 SOI衬底具有具有第一和第二导电类型层,绝缘层和半导体层的半导体衬底。 第一元件隔离绝缘层被埋在SOI衬底中,具有到达第一导电类型层的下端,并且将第一元件区域与第二元件区域隔离。 第一和第二导电类型晶体管分别位于第一和第二元件区域中,并且在半导体层中形成有各自的沟道区。 第一和第二背栅极触点分别耦合到第一和第二元件区域中的第二导电类型层。

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