公开(公告)号：US06740580B1

公开(公告)日：2004-05-25

申请号：US09389633

申请日：1999-09-03

申请人： Subhash Gupta ,  Chyi S. Chern ,  Mei Sheng Zhou

发明人： Subhash Gupta ,  Chyi S. Chern ,  Mei Sheng Zhou

IPC分类号： H01L214763

CPC分类号： H01L21/76846 ,  H01L21/76873 ,  H01L21/76874 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method to form copper interconnects is described. The method may be used to form single or dual damascene interconnects. The addition of an aluminum barrier layer to the conventional barrier layer creates a superior barrier to copper diffusion. A substrate layer is provided. A dielectric layer is deposited overlying the substrate layer. The dielectric layer patterned to form interconnect trenches. An optional titanium adhesion layer may be deposited. An aluminum barrier layer is deposited overlying the interior surfaces of the trenches. A second barrier layer, comprising for instance titanium and titanium nitride, is deposited overlying the aluminum barrier layer. A copper layer is deposited overlying the second barrier layer and filling the interconnect trenches. The copper layer, the second barrier layer, and the aluminum barrier layer are polished down to the top surface of the dielectric layer to define the copper interconnects, and complete the fabrication of the integrated circuit device.

摘要翻译： 描述形成铜互连的方法。 该方法可以用于形成单镶嵌或双镶嵌互连。 向常规阻挡层添加铝阻挡层产生对铜扩散的优异屏障。 提供基底层。 沉积在基底层上的电介质层。 图案化的电介质层形成互连沟槽。 可以沉积可选的钛粘合层。 覆盖在沟槽的内表面上的铝阻挡层被沉积。 包含例如钛和氮化钛的第二阻挡层沉积在铝阻挡层上。 沉积铜层，覆盖第二阻挡层并填充互连沟槽。 铜层，第二阻挡层和铝阻挡层被抛光到介电层的顶表面以限定铜互连，并且完成集成电路器件的制造。

公开(公告)号：US06664153B2

公开(公告)日：2003-12-16

申请号：US10072099

申请日：2002-02-08

申请人： Chew Hoe Ang ,  Eng Hua Lim ,  Randall Cher Liang Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

发明人： Chew Hoe Ang ,  Eng Hua Lim ,  Randall Cher Liang Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

IPC分类号： H01L21336

CPC分类号： H01L29/4983 ,  H01L21/28035

摘要： A method for forming a single gate having a dual work-function is described. A gate electrode is formed overlying a gate dielectric layer on a substrate. Sidewalls of the gate electrode are selectively doped whereby the doped sidewalls have a first work-function and whereby a central portion of the gate electrode not doped has a second work-function to complete formation of a single gate having multiple work-functions in the fabrication of integrated circuits.

摘要翻译： 描述了一种形成具有双功能功能的单门的方法。 在基板上形成覆盖栅介质层的栅电极。 栅电极的侧壁被选择性掺杂，由此掺杂侧壁具有第一功函数，并且由此未掺杂的栅电极的中心部分具有第二功函数，以在制造中完成形成具有多个功函数的单个栅极 的集成电路。

公开(公告)号：US06656643B2

公开(公告)日：2003-12-02

申请号：US09785116

申请日：2001-02-20

申请人： Subhash Gupta ,  Mei Sheng Zhou

发明人： Subhash Gupta ,  Mei Sheng Zhou

IPC分类号： G03F900

CPC分类号： B82Y10/00 ,  B82Y40/00 ,  G03F1/24 ,  G03F1/54

摘要： An EUV photolithographic mask device and a method of fabricating the same. The EUV photolithographic mask comprises a multi-layer over an EUV masking substrate and a patterned light absorbing layer formed on the multi-layer. The method comprises the steps of forming a multi-layer on an EUV mask substrate, forming a light absorbing layer on the multi-layer, and etching an opening through the light absorbing layer to the multi-layer. The light absorbing layer includes a metal selected from the group comprising nickel, chromium, cobalt, and alloys thereof, and is preferably nickel.

公开(公告)号：US06521539B1

公开(公告)日：2003-02-18

申请号：US09303837

申请日：1999-05-03

申请人： Mei Sheng Zhou ,  Xue Chun Dai ,  Chiew Wah Yap

发明人： Mei Sheng Zhou ,  Xue Chun Dai ,  Chiew Wah Yap

IPC分类号： H01L21302

CPC分类号： H01L29/66545 ,  H01L21/31116 ,  H01L21/31138

摘要： A method for forming a patterned microelectronic layer. There is first provided a substrate. There is then formed over the substrate a multi-layer stack layer comprising: (1) a first lower microelectronic layer; (2) a second intermediate patterned microelectronic layer formed over the first lower microelectronic layer; and (3) a third upper patterned microelectronic layer formed over the second intermediate patterned microelectronic layer, where the first lower microelectronic layer and the third upper patterned microelectronic layer are susceptible to etching within a first etchant. There is then formed encapsulating the first lower microelectronic layer and at least portion of the second intermediate patterned microelectronic layer while leaving exposed at least a portion of the third upper patterned microelectronic layer an encapsulating layer. There is then etched selectively, while employing a first etch method which employs the first etchant, the third upper patterned microelectronic layer while the first lower microelectronic layer and at least the portion of the second intermediate patterned microelectronic layer are encapsulated with the encapsulating layer. Finally, there is then stripped, while employing a second etch method which employs a second etchant, from the first microelectronic layer and at least the portion of the second intermediate patterned microelectronic layer the encapsulating layer. The method may be employed for stripping from a gate electrode within a field effect transistor (FET) a patterned dielectric cap layer formed upon the gate electrode while not etching a gate dielectric layer upon Which is formed the gate electrode within the field effect transistor (FET).

摘要翻译： 一种用于形成图案化微电子层的方法。 首先提供基板。 然后在衬底上形成多层堆叠层，其包括：（1）第一下部微电子层; （2）形成在第一下部微电子层上的第二中间图案化微电子层; 和（3）在第二中间图案化微电子层上形成的第三上图形微电子层，其中第一下微电子层和第三上图形微电子层易于在第一蚀刻剂内蚀刻。 然后形成封装第一下部微电子层和第二中间图案化微电子层的至少部分，同时将第三上部图案化微电子层的至少一部分暴露于封装层。 然后选择性地蚀刻，同时使用采用第一蚀刻剂的第一蚀刻方法，第三上图案化微电子层，而第一下微电子层和第二中间图案化微电子层的至少部分用封装层封装。 最后，然后剥离，同时采用采用第二蚀刻剂的第二蚀刻方法，从第一微电子层和第二中间图案化微电子层的至少部分封装层。 该方法可用于从场效应晶体管（FET）内的栅电极剥离形成在栅电极上的图案化电介质盖层，同时不蚀刻在场效应晶体管（FET）内形成栅电极的栅极电介质层 ）。

公开(公告)号：US06429109B1

公开(公告)日：2002-08-06

申请号：US10017953

申请日：2001-12-14

申请人： Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen ,  Chew Hoe Ang ,  Eng Hua Lim ,  Randall Cha

发明人： Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen ,  Chew Hoe Ang ,  Eng Hua Lim ,  Randall Cha

IPC分类号： H01L214763

CPC分类号： H01L21/28194 ,  H01L21/28097 ,  H01L21/28176 ,  H01L21/28238 ,  H01L29/513 ,  H01L29/517

摘要： A method of forming a gate comprising the following steps. A substrate is provided. A pre-gate structure is formed over the substrate. The pregate structure includes a sacrificial metal layer between an upper gate conductor layer and a lower gate dielectric layer. The pre-gate structure is annealed to form the gate. The gate comprising: an upper silicide layer formed from a portion of the sacrificial metal layer and a portion of the upper gate conductor layer from the anneal; and a lower metal oxide layer formed from a portion of the gate dielectric layer and a portion of the sacrificial metal layer from the anneal.

摘要翻译： 一种形成浇口的方法，包括以下步骤。 提供基板。 在衬底上形成预栅极结构。 预栅结构包括在上栅极导体层和下栅极介电层之间的牺牲金属层。 预栅结构退火形成栅极。 该栅极包括：由牺牲金属层的一部分形成的上硅化物层和来自退火的上部栅极导体层的一部分; 以及由栅极电介质层的一部分和来自退火的牺牲金属层的一部分形成的下部金属氧化物层。

公开(公告)号：US06274499B1

公开(公告)日：2001-08-14

申请号：US09442493

申请日：1999-11-19

申请人： Subhash Gupta ,  Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

发明人： Subhash Gupta ,  Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Ramasamy Chockalingam

IPC分类号： H01L21302

CPC分类号： H01L21/76801 ,  H01L21/3212 ,  H01L21/32134 ,  H01L21/76807 ,  H01L21/76834

摘要： In accordance with the objects of this invention a new method to prevent copper contamination of the intermetal dielectric layer during etching, CMP, or post-etching and post-CMP cleaning by forming a dielectric cap for isolation of the underlying dielectric layer is described. In one embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A via is patterned and filled with a metal layer and planarized. A copper layer is deposited overlying the planarized metal layer and dielectric cap layer. The copper layer is etched to form a copper line wherein the dielectric cap layer prevents copper contamination of the dielectric layer during etching and cleaning. In another embodiment of the invention, a dielectric layer is provided overlying a semiconductor substrate. A dielectric cap layer is deposited overlying the dielectric layer. A dual damascene opening is formed through the dielectric cap layer and the dielectric layer. A copper layer is deposited overlying a barrier metal layer over the dielectric cap layer and filling the dual damascene opening. The copper layer is polished back to leave the copper layer only within the dual damascene opening where the dielectric cap layer prevents copper contamination of the dielectric layer during polishing and cleaning.

摘要翻译： 根据本发明的目的，描述了通过形成用于隔离下面介电层的电介质盖，在蚀刻，CMP或后蚀刻和后CMP清洗中防止金属间电介质层的铜污染的新方法。 在本发明的一个实施例中，提供覆盖在半导体衬底上的电介质层。 介电覆盖层沉积在介电层上。 通孔被图案化并填充有金属层并且被平坦化。 沉积在平坦化的金属层和电介质盖层上的铜层。 铜层被蚀刻以形成铜线，其中电介质盖层在蚀刻和清洁期间防止电介质层的铜污染。 在本发明的另一个实施例中，提供覆盖半导体衬底的电介质层。 介电覆盖层沉积在介电层上。 通过电介质盖层和电介质层形成双镶嵌开口。 将铜层沉积在电介质盖层上方的阻挡金属层上，并填充双镶嵌开口。 将铜层抛光回来，仅在双镶嵌开口中留下铜层，其中介电盖层在抛光和清洁期间防止电介质层的铜污染。

公开(公告)号：US06251786B1

公开(公告)日：2001-06-26

申请号：US09390783

申请日：1999-09-07

申请人： Mei Sheng Zhou ,  Paul Kwok Keung Ho ,  Subhash Gupta

发明人： Mei Sheng Zhou ,  Paul Kwok Keung Ho ,  Subhash Gupta

IPC分类号： H01L2100

CPC分类号： H01L21/76834 ,  H01L21/3212 ,  H01L21/76807 ,  H01L21/7684 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A dual damascene structure is created in a dielectric layer, the structure contains a barrier layer while a cap layer may or may not be provided over the layer of dielectric for further protection of the dual damascene structure. The surface of the copper in the dual damascene structure is recessed, a thin film is deposited and planarized/partially removed by either CMP or a plasma etch thereby providing a sturdy surface above the copper of the dual damascene structure that prevents dishing and erosion of this surface.

摘要翻译： 在电介质层中产生双镶嵌结构，该结构包含阻挡层，而覆盖层可以设置在电介质层上，也可以不设置在电介质层上，以进一步保护双镶嵌结构。 双镶嵌结构中的铜的表面是凹进的，通过CMP或等离子体蚀刻沉积并平面化/部分去除薄膜，从而在双镶嵌结构的铜上方提供坚固的表面，防止该镶嵌结构的凹陷和侵蚀 表面。

公开(公告)号：US06184138B2

公开(公告)日：2001-02-06

申请号：US09390782

申请日：1999-09-07

申请人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta

发明人： Paul Kwok Keung Ho ,  Mei Sheng Zhou ,  Subhash Gupta

IPC分类号： H01L2144

CPC分类号： H01L21/76843 ,  H01L21/7684 ,  H01L21/76874 ,  H01L21/76876 ,  H01L21/76877 ,  H01L21/76879

摘要： A new method is provided to construct a copper dual damascene structure. A layer of IMD is deposited over the surface of a substrate. A cap layer is deposited over this layer of IMD, the dual damascene structure is then patterned through the cap layer and into the layer of IMD. A barrier layer is blanket deposited, a copper seed layer is deposited over the barrier layer. The dual damascene structure is then filled with a spin-on material. The barrier layer and the copper seed layer are removed above the cap layer; the cap layer can be partially removed or can be left in place. The spin on material remains in place in the via and trench opening during the operation of removing the copper seed layer and the barrier layer from above the cap surface thereby protecting the inside surfaces of these openings. The spin-on material is next removed from the dual damascene structure and copper is deposited. The cap layer that is still present above the surface of the IMD protects the dielectric from being contaminated with copper solution during the deposition of the copper. The excess copper is removed using a touch-up CMP. The cap layer over the surface of the IMD can, after the copper has been deposited, be removed if this is so desired. As a final step in the process, a liner or oxidation/diffusion protection layer is deposited over the dual damascene structure and its surrounding area.

摘要翻译： 提供了一种构建铜双镶嵌结构的新方法。 一层IMD沉积在衬底的表面上。 覆盖层沉积在IMD的该层上，然后将双镶嵌结构通过盖层图案化并进入IMD层。 阻挡层被覆盖沉积，铜晶种层沉积在阻挡层上。 然后用镶嵌材料填充双镶嵌结构。 在盖层上除去阻挡层和铜籽晶层; 盖层可以被部分地去除或可以留在原处。 在从盖表面上方去除铜种子层和阻挡层的操作期间，材料上的旋转保持在通孔和沟槽开口中的适当位置，从而保护这些开口的内表面。 随后从双镶嵌结构中去除旋涂材料，并沉积铜。 仍然存在于IMD表面之上的盖层保护铜在沉积期间不被铜溶液污染。 使用上层CMP去除多余的铜。 如果这样做是希望的话，在沉积铜之后，IMD表面上的盖层可以被去除。 作为该方法的最后一步，衬垫或氧化/扩散保护层沉积在双镶嵌结构及其周围区域上。

公开(公告)号：US5866448A

公开(公告)日：1999-02-02

申请号：US902757

申请日：1997-07-30

申请人： Yelehanka Ramachandramurthy Pradeep ,  Tang Kok Hiang ,  Mei Sheng Zhou

发明人： Yelehanka Ramachandramurthy Pradeep ,  Tang Kok Hiang ,  Mei Sheng Zhou

IPC分类号： H01L21/336 ,  H01L21/8238

CPC分类号： H01L29/6659 ,  H01L21/823814 ,  Y10S438/963

摘要： A method for fabrication of a lightly-doped-drain (LDD) structure for self aligned polysilicon gate MOSFETs is described wherein a polymer layer, formed along the sidewall during the patterning process of the polysilicon gate electrode, is used to mask the source/drain ion implant. The sidewall polymer layer replaces the conventional silicon oxide sidewall as an LDD spacer and offers improved thickness control as well as an improved sequence of processing steps whereby the deposition of a spacer oxide layer onto the gate oxide is eliminated. A cap oxide layer first deposited over the gate polysilicon layer. This oxide layer is then patterned and etched using RIE under conditions which form a polymer sidewall layer along the edges of the cap oxide pattern. The polysilicon layer is then etched, and has a pattern concentric with the cap oxide pattern but wider by the thickness of the polymer sidewall. After removal of the polymer and residual photoresist, the source/drain implant is performed, followed by removal of the polysilicon lip by RIE using the cap oxide as a mask. The LDD implant is then performed.

摘要翻译： 描述了一种制造用于自对准多晶硅栅极MOSFET的轻掺杂漏极（LDD）结构的方法，其中在多晶硅栅电极的图案化工艺期间沿侧壁形成的聚合物层用于掩蔽源/漏 离子植入。 侧壁聚合物层代替常规的氧化硅侧壁作为LDD间隔物，并提供改进的厚度控制以及改进的处理步骤顺序，从而消除间隔氧化物层沉积到栅极氧化物上。 首先沉积在栅极多晶硅层上的覆盖氧化物层。 然后使用RIE在沿着氧化物图案的边缘形成聚合物侧壁层的条件下对该氧化物层进行构图和蚀刻。 然后蚀刻多晶硅层，并且具有与盖氧化物图案同心的图案，但是通过聚合物侧壁的厚度更宽。 在去除聚合物和残余光致抗蚀剂之后，进行源极/漏极注入，随后通过RIE使用帽氧化物作为掩模去除多晶硅唇缘。 然后执行LDD植入。

公开(公告)号：US5801083A

公开(公告)日：1998-09-01

申请号：US954046

申请日：1997-10-20

申请人： Bo Yu ,  Qing Hua Zhong ,  Jian Hui Ye ,  Mei Sheng Zhou

发明人： Bo Yu ,  Qing Hua Zhong ,  Jian Hui Ye ,  Mei Sheng Zhou

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76232 ,  Y10S148/05 ,  Y10S148/161 ,  Y10S438/978

摘要： A method for forming insulator filled, shallow trench isolation regions, with rounded corners, has been developed. The process features the use of a polymer coated opening, in an insulator layer, used as a mask to define the shallow trench region in silicon. After completion of the shallow trench formation the polymer spacers are removed, exposing a region of unetched semiconductor, that had been protected by the polymer spacers, during the shallow trench dry etching procedure. The sharp corner, at the intersection between the shallow trench and the unetched region of semiconductor, is then converted to a rounded corner, via thermal oxidation of exposed silicon surfaces. The polymer spacers also eliminate the top corner wraparound.

摘要翻译： 已经开发了用于形成具有圆角的绝缘体填充的浅沟槽隔离区域的方法。 该方法的特征在于在绝缘体层中使用聚合物涂布的开口，用作掩模以限定硅中的浅沟槽区域。 在浅沟槽形成完成之后，去除聚合物间隔物，暴露在浅沟槽干法蚀刻过程中被聚合物间隔物保护的未蚀刻半导体区域。 然后，通过暴露的硅表面的热氧化，在浅沟槽和半导体的未蚀刻区域之间的交叉点处的尖角被转换成圆角。 聚合物间隔物也消除了顶角环绕​​。