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11 条记录 (耗时 0.028 秒)

    Method of fabricating variable length vertical transistors
    1.
    发明授权
    Method of fabricating variable length vertical transistors 失效
    制造可变长度垂直晶体管的方法

    公开(公告)号：US06632712B1

    公开(公告)日：2003-10-14

    申请号：US10263895

    申请日：2002-10-03

    申请人： Chew-Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

    发明人： Chew-Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

    IPC分类号： H01L218238

    CPC分类号： H01L29/66666 ,  H01L21/823885 ,  H01L29/7827

    摘要： A process for fabricating vertical CMOS devices, featuring variable channel lengths, has been developed. Channel region openings are defined in composite insulator stacks, with the channel length of specific devices determined by the thickness of the composite insulator stack. Selective removal of specific components of the composite insulator stack, in a specific region, allows the depth of the channel openings to be varied. A subsequent epitaxial silicon growth procedure fills the variable depth channel openings, providing the variable length, channel regions for the vertical CMOS devices.

    摘要翻译： 已经开发了用于制造具有可变通道长度的垂直CMOS器件的工艺。 通道区域开口限定在复合绝缘体堆叠中，特定器件的通道长度由复合绝缘子堆叠的厚度确定。 在特定区域中选择性去除复合绝缘子堆叠的特定部件允许沟道开口的深度变化。 随后的外延硅生长过程填充可变深度通道开口，为垂直CMOS器件提供可变长度的沟道区。

    Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers
    2.
    发明授权
    Method to form an asymmetrical non-volatile memory device using small in-situ doped polysilicon spacers 失效
    使用小的原位掺杂多晶硅间隔物形成非对称非易失性存储器件的方法

    公开(公告)号：US06544848B1

    公开(公告)日：2003-04-08

    申请号：US10224212

    申请日：2002-08-20

    申请人： Chew Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

    发明人： Chew Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia Zhen Zheng ,  Elgin Quek ,  Mei Sheng Zhou ,  Daniel Yen

    IPC分类号： H01L218247

    CPC分类号： H01L29/66825 ,  H01L21/28273

    摘要： A new method of forming a sharp tip on a floating gate in the fabrication of a EEPROM memory cell is described. A first gate dielectric layer is provided on a substrate. A second gate dielectric layer is deposited overlying the first gate dielectric layer. A floating gate/control gate stack is formed overlying the second gate dielectric layer. One sidewall portion of the floating gate is covered with a mask. The second gate dielectric layer not covered by the mask is etched away whereby an undercut of the floating gate is formed in the second gate dielectric layer. The mask is removed. Polysilicon spacers are formed on sidewalls of the floating gate wherein one of the polysilicon spacers fills the undercut thereby forming a sharp polysilicon tip to improve the erase efficiency of the memory cell.

    摘要翻译： 描述了在EEPROM存储器单元的制造中在浮动栅极上形成尖端尖端的新方法。 第一栅介质层设置在基板上。 第二栅介质层沉积在第一栅介质层上。 形成覆盖在第二栅极电介质层上的浮栅/控制栅叠层。 浮动栅极的一个侧壁部分被掩模覆盖。 被掩模未被覆盖的第二栅极电介质层被蚀刻掉，从而在第二栅极介质层中形成浮栅的底切。 去除面具。 多晶硅间隔物形成在浮置栅极的侧壁上，其中多晶硅间隔物中的一个填充底切，从而形成尖锐的多晶硅尖端，以提高存储单元的擦除效率。

    Method to pattern small features by using a re-flowable hard mask
    3.
    发明授权
    Method to pattern small features by using a re-flowable hard mask 有权
    通过使用可重新流动的硬掩模来绘制小特征的方法

    公开(公告)号：US06828082B2

    公开(公告)日：2004-12-07

    申请号：US10072102

    申请日：2002-02-08

    申请人： Chew-Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia-Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

    发明人： Chew-Hoe Ang ,  Eng Hua Lim ,  Randall Cha ,  Jia-Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

    IPC分类号： G03F700

    CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/31144

    摘要： A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “1”. The re-flowed first opening lower width “1” being less than the pre-reflowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “1”. Removing the patterned, re-flowed masking layer. A small feature material is then formed within the second opening and any excess small feature material above the etched spacing layer is removed. The etched spacing layer is removed to form the small feature comprised of the small feature material.

    摘要翻译： 一种形成小特征的方法，包括以下步骤。 提供其上形成有介电层的基板。 在电介质层上形成间隔层。 间隔层的厚度等于要形成的小特征的厚度。 在间隔层上形成图案化的可重新流动的掩模层。 掩模层具有宽度“L”的第一开口。 图案化的可再流过的掩模层被再流动以形成具有较低宽度“1”的具有再流动的第一开口的图案化的再流过的掩蔽层。 再流通的第一开口下部宽度“1”小于预先回流的第一开口宽度“L”。 使用图案化的再流过的掩模层作为掩模将间隔层蚀刻到介电层，以在蚀刻的间隔层内形成具有等于再流动的第一开口下宽度“1”的宽度的第二开口。 去除图案化的再流过的掩蔽层。 然后在第二开口内形成小的特征材料，并且去除蚀刻的间隔层上方的任何过量的小特征材料。 蚀刻的间隔层被去除以形成由小特征材料组成的小特征。

    Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask
    4.
    发明授权
    Method of forming small transistor gates by using self-aligned reverse spacer as a hard mask 有权
    通过使用自对准反向间隔件作为硬掩模形成小晶体管栅极的方法

    公开(公告)号：US06610604B1

    公开(公告)日：2003-08-26

    申请号：US10068053

    申请日：2002-02-05

    申请人： Chew-Hoe Ang ,  Eng-Hua Lim ,  Randall Cha ,  Jia-Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

    发明人： Chew-Hoe Ang ,  Eng-Hua Lim ,  Randall Cha ,  Jia-Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

    IPC分类号： H01L21302

    CPC分类号： H01L21/28132

    摘要： A method of forming narrow gates comprising the following steps. A substrate is provided having an overlying Si3N4 or an SiO2/Si3N4 stack gate dielectric layer. A gate material layer is formed over the gate dielectric layer. A hard mask layer is formed over the gate material layer. The hard mask layer and the gate material layer are patterned to form a hard mask/gate material layer stack. A planarized dielectric layer is formed surrounding the hard mask/gate material layer stack. The patterned hard mask layer is removed from over the patterned gate material layer to form a cavity having exposed dielectric layer side walls. Masking spacers are formed on the exposed dielectric layer side walls over a portion of the patterned gate material layer. The patterned gate material layer is etched using the masking spacers as masks to expose a portion of the gate dielectric layer. The planarized dielectric layer is removed. The masking spacers are removed to form narrow gates comprising gate material.

    摘要翻译： 一种形成窄门的方法，包括以下步骤。 提供具有覆盖的Si 3 N 4或SiO 2 / Si 3 N 4堆叠栅极介电层的衬底。 栅极材料层形成在栅极介电层上。 在栅极材料层上形成硬掩模层。 图案化硬掩模层和栅极材料层以形成硬掩模/栅极材料层堆叠。 形成围绕硬掩模/栅极材料层叠层的平坦化介电层。 图案化的硬掩模层从图案化的栅极材料层上去除以形成具有暴露的电介质层侧壁的空腔。 屏蔽间隔物形成在图案化栅极材料层的一部分上的暴露的电介质层侧壁上。 使用掩模间隔物作为掩模蚀刻图案化的栅极材料层，以露出栅极电介质层的一部分。 去除平坦化的介电层。 去除掩模间隔物以形成包括栅极材料的窄门。

    Method to pattern small features by using a re-flowable hard mask
    6.
    发明申请
    Method to pattern small features by using a re-flowable hard mask 审中-公开
    通过使用可再流动的硬掩模来绘制小特征的方法

    公开(公告)号：US20050089777A1

    公开(公告)日：2005-04-28

    申请号：US10988349

    申请日：2004-11-12

    申请人： Chew-Hoe Ang ,  Eng Lim ,  Randall Cha ,  Jia-Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

    发明人： Chew-Hoe Ang ,  Eng Lim ,  Randall Cha ,  Jia-Zhen Zheng ,  Elgin Quek ,  Mei-Sheng Zhou ,  Daniel Yen

    IPC分类号： G03C5/00 ,  G03F7/00 ,  G03F7/26 ,  H01L21/033 ,  H01L21/311 ,  H01L21/76

    CPC分类号： H01L21/0338 ,  H01L21/0337 ,  H01L21/31144

    摘要： A method of forming small features, comprising the following steps. A substrate having a dielectric layer formed thereover is provided. A spacing layer is formed over the dielectric layer. The spacing layer has a thickness equal to the thickness of the small feature to be formed. A patterned, re-flowable masking layer is formed over the spacing layer. The masking layer having a first opening with a width “L”. The patterned, re-flowable masking layer is re-flowed to form a patterned, re-flowed masking layer having a re-flowed first opening with a lower width “l”. The re-flowed first opening lower width “l” being less than the pre-re-flowed first opening width “L”. The spacing layer is etched down to the dielectric layer using the patterned, re-flowed masking layer as a mask to form a second opening within the etched spacing layer having a width equal to the re-flowed first opening lower width “l”. Removing the patterned, re-flowed masking layer. A small feature material is then formed within the second opening and any excess small feature material above the etched spacing layer is removed. The etched spacing layer is removed to form the small feature comprised of the small feature material.

    摘要翻译： 一种形成小特征的方法，包括以下步骤。 提供其上形成有介电层的基板。 在电介质层上形成间隔层。 间隔层的厚度等于要形成的小特征的厚度。 在间隔层上形成图案化的可重新流动的掩模层。 掩模层具有宽度“L”的第一开口。 图案化的可重新流动的掩模层被再流动以形成具有较低宽度“l”的具有再流动的第一开口的图案化的再流过的掩蔽层。 再流出的第一开口下部宽度“l”小于预先流动的第一开口宽度“L”。 使用图案化的再流过的掩模层作为掩模将间隔层蚀刻到介电层上，以在蚀刻的间隔层内形成具有等于再流动的第一开口下宽度“l”的宽度的第二开口。 去除图案化的再流过的掩蔽层。 然后在第二开口内形成小的特征材料，并且去除蚀刻的间隔层上方的任何过量的小特征材料。 蚀刻的间隔层被去除以形成由小特征材料组成的小特征。

    Salicide method for producing a semiconductor device using silicon/amorphous silicon/metal structure
    8.
    发明授权
    Salicide method for producing a semiconductor device using silicon/amorphous silicon/metal structure 失效
    用于制造使用硅/非晶硅/金属结构的半导体器件的硅化物方法

    公开(公告)号：US06534390B1

    公开(公告)日：2003-03-18

    申请号：US10050444

    申请日：2002-01-16

    申请人： Yung Fu Chong ,  Randall Cha ,  Kin Leong Pey

    发明人： Yung Fu Chong ,  Randall Cha ,  Kin Leong Pey

    IPC分类号： H01L213205

    CPC分类号： H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/3212 ,  H01L29/41783 ,  H01L29/66545

    摘要： The present invention provides an improved semiconductor device of a Silicon/Amorphous Silicon/Metal Structure (SASM) and a method of making an improved semiconductor device by a salicide process by using an anneal to form a thick silicide film on shallow source/drain regions and a chemical-mechanical polish (CMP) step is then performed to remove the silicide over the top of the spacers at the gate, thus breaking the continuity of the silicide film extending from the gate to the source drain region.

    摘要翻译： 本发明提供一种硅/非晶硅/金属结构（SASM）的改进的半导体器件以及通过使用退火在硅源/漏区上形成厚硅化物膜而通过自对准硅化物工艺制造改进的半导体器件的方法， 然后执行化学机械抛光（CMP）步骤以在栅极处去除间隔物的顶部上的硅化物，从而破坏从栅极延伸到源极漏极区的硅化物膜的连续性。

    Method to fabricate dish-free copper interconnects
    9.
    发明授权
    Method to fabricate dish-free copper interconnects 失效
    制造无盘铜互连的方法

    公开(公告)号：US06531386B1

    公开(公告)日：2003-03-11

    申请号：US10072107

    申请日：2002-02-08

    申请人： Victor Seng-Keong Lim ,  Simon Chooi ,  Randall Cha

    发明人： Victor Seng-Keong Lim ,  Simon Chooi ,  Randall Cha

    IPC分类号： H01L214763

    CPC分类号： H01L21/76885 ,  H01L21/76852 ,  H01L21/76879

    摘要： A method of fabricating at least one metal interconnect including the following steps. A structure having at least one exposed conductive structure is provided. A non-stick material layer is formed over the structure and the at least one exposed conductive structure. The non-stick material layer having an upper surface. The non-stick material layer is patterned to form a patterned non-stick material layer having at least one trench therethrough exposing at least a portion of the at least one conductive structure. A metal interconnect is formed in contact with the exposed portion of the at least one conductive structure within the at least one trench wherein the non-stick properties of the patterned non-stick material layer prevent accumulation of the metal comprising the metal interconnect upon the patterned upper surface of the patterned non-stick material layer. The at least one metal interconnect having an upper surface. The patterned non-stick material layer is removed. A planarized dielectric layer is formed over the structure exposing the upper surface of the at least one metal interconnect.

    摘要翻译： 一种制造至少一种金属互连的方法，包括以下步骤。 提供具有至少一个暴露的导电结构的结构。 在结构和至少一个暴露的导电结构上形成不粘材料层。 不粘材料层具有上表面。 将不粘材料层图案化以形成图案化的不粘材料层，其具有通过其暴露出至少一部分导电结构的至少一个沟槽。 在所述至少一个沟槽内形成与所述至少一个导电结构的所述暴露部分接触的金属互连，其中所述图案化不粘材料层的不粘性能防止包含所述金属互连的所述金属在图案化 图案化不粘材料层的上表面。 所述至少一个金属互连具有上表面。 去除图案化的不粘材料层。 在暴露至少一个金属互连的上表面的结构之上形成平坦化的介电层。