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    Methods of Forming Memory Cells and Arrays
    81.
    发明申请
    Methods of Forming Memory Cells and Arrays 有权
    形成记忆单元和阵列的方法

    公开(公告)号：US20150028283A1

    公开(公告)日：2015-01-29

    申请号：US13948980

    申请日：2013-07-23

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Giorgio Servalli ,  Carmela Cupeta ,  Fabio Pellizzer

    IPC: H01L45/00

    CPC classification number: H01L45/1293 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1286 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1608 ,  H01L45/1666 ,  H01L45/1675

    Abstract: Some embodiments include methods of forming memory cells. Heater structures are formed over an array of electrical nodes, and phase change material is formed across the heater structures. The phase change material is patterned into a plurality of confined structures, with the confined structures being in one-to-one correspondence with the heater structures and being spaced from one another by one or more insulative materials that entirely laterally surround each of the confined structures. Some embodiments include memory arrays having heater structures over an array of electrical nodes. Confined phase change material structures are over the heater structures and in one-to-one correspondence with the heater structures. The confined phase change material structures are spaced from one another by one or more insulative materials that entirely laterally surround each of the confined phase change material structures.

    Abstract translation: 一些实施例包括形成存储器单元的方法。 加热器结构形成在电节点阵列上，相变材料跨过加热器结构形成。 相变材料被图案化成多个限制结构，其中限制结构与加热器结构一一对应，并且通过一个或多个完全横向围绕每个限制结构的绝缘材料彼此间隔开 。 一些实施例包括在电节点阵列上具有加热器结构的存储器阵列。 密闭相变材料结构在加热器结构之上，并且与加热器结构一一对应。 受限制的相变材料结构通过一个或多个完全横向围绕每个限定相变材料结构的绝缘材料彼此间隔开。

    MEMORY CONSTRUCTIONS
    82.
    发明申请
    MEMORY CONSTRUCTIONS 有权
    记忆结构

    公开(公告)号：US20140110657A1

    公开(公告)日：2014-04-24

    申请号：US13658676

    申请日：2012-10-23

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Andrea Redaelli ,  Agostino Pirovano

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/00 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144

    Abstract: Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors.

    Abstract translation: 一些实施例包括在顶部和底部导电材料之间具有多个带的记忆结构。 这些带包括与非硫属化物带交替的硫属化物带。 在一些实施方案中，可以存在至少两个硫族化物带和至少一个非硫族化物带。 在一些实施例中，存储器单元可以在一对电极之间; 其中一个电极被配置为喷枪，倾斜板，容器或梁。 在一些实施例中，存储器单元可以与诸如二极管，场效应晶体管或双极结型晶体管的选择器件电耦合。

    ACCESS LINE FORMATION FOR A MEMORY ARRAY
    83.
    发明申请
    ACCESS LINE FORMATION FOR A MEMORY ARRAY 有权

    公开(公告)号：US20250031383A1

    公开(公告)日：2025-01-23

    申请号：US18788475

    申请日：2024-07-30

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Anna Maria Conti

    IPC: H10B63/00 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H10B53/20 ,  H10N70/00 ,  H10N70/20

    Abstract: Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.

    Three dimensional memory array
    86.
    发明授权
    Three dimensional memory array 有权

    公开(公告)号：US11587979B2

    公开(公告)日：2023-02-21

    申请号：US17144669

    申请日：2021-01-08

    Applicant: Micron Technology, Inc.

    Inventor： Fabio Pellizzer ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: The present disclosure includes three dimensional memory arrays, and methods of processing the same. A number of embodiments include a plurality of conductive lines separated from one other by an insulation material, a plurality of conductive extensions arranged to extend substantially perpendicular to the plurality of conductive lines, and a storage element material formed around each respective one of the plurality of conductive extensions and having two different contacts with each respective one of the plurality of conductive lines, wherein the two different contacts with each respective one of the plurality of conductive lines are at two different ends of that respective conductive line.

    Techniques for forming self-aligned memory structures
    88.
    发明授权
    Techniques for forming self-aligned memory structures 有权

    公开(公告)号：US11417841B2

    公开(公告)日：2022-08-16

    申请号：US16539932

    申请日：2019-08-13

    Applicant: Micron Technology, Inc.

    Inventor： Stephen W. Russell ,  Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Lorenzo Fratin

    IPC: H01L45/00 ,  H01L27/24

    Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

    ACCESS LINE FORMATION FOR A MEMORY ARRAY
    89.
    发明申请
    ACCESS LINE FORMATION FOR A MEMORY ARRAY 有权

    公开(公告)号：US20220165795A1

    公开(公告)日：2022-05-26

    申请号：US17671373

    申请日：2022-02-14

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Anna Maria Conti

    IPC: H01L27/24 ,  H01L21/3213 ,  H01L21/768 ,  H01L45/00 ,  H01L23/528 ,  H01L27/11514

    Abstract: Methods, systems, and devices for access line formation for a memory array are described. The techniques described herein may be used to fabricate access lines for one or more decks of a memory array. In some examples, one or more access lines of a deck may be formed using an independent processing step. For example, different fabrication processes may be used to form a plurality of access lines in a deck and to form the pillars (e.g., the memory cells) that are coupled with the access lines. In some examples, an offset between the access lines and the pillars may exist due to the components being fabricated in different processing steps.

    Arrays of memory cells and methods of forming an array of elevationally-outer-tier memory cells and elevationally-inner-tier memory cells
    90.
    发明授权
    Arrays of memory cells and methods of forming an array of elevationally-outer-tier memory cells and elevationally-inner-tier memory cells 有权

    公开(公告)号：US11302748B2

    公开(公告)日：2022-04-12

    申请号：US16575743

    申请日：2019-09-19

    Applicant: Micron Technology, Inc.

    Inventor： Anna Maria Conti ,  Agostino Pirovano ,  Andrea Redaelli

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A method of forming an array of memory cells, where the array comprises an elevationally-inner tier of memory cells comprising spaced-inner-tier-lower-first-conductive lines and inner-tier-programmable material directly there-above, an elevationally-outer tier of memory cells comprising spaced-outer-tier-lower-first-conductive lines and outer-tier-programmable material directly there-above, and spaced-upper-second-conductive lines that are electrically shared by the outer-tier memory cells and the inner-tier memory cells, comprises depositing conductor material for all of the shared-spaced-upper-second-conductive lines. All of the conductor material for all of the shared-spaced-upper-second-conductive lines is patterned using only a single masking step. Other method embodiments and arrays of memory cells independent of method of manufacture are disclosed.

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