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公开(公告)号：US12255143B2
公开(公告)日：2025-03-18
申请号：US17187481
申请日：2021-02-26
Applicant: Micron Technology, Inc.
Inventor： Alyssa N. Scarbrough , Jordan D. Greenlee , John D. Hopkins
IPC: H01L23/532 , H01L23/528 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/27 , H10B43/35 , H10B43/40
Abstract: A microelectronic device includes a stack structure, a staircase structure, composite pad structures, and conductive contact structures. The stack structure includes vertically alternating conductive structures and insulative structures arranged in tiers. Each of the tiers individually includes one of the conductive structures and one of the insulative structures. The staircase structure has steps including edges of at least some of the tiers of the stack structure. The composite pad structures are on the steps of the staircase structure. Each of the composite pad structures includes a lower pad structure, and an upper pad structure overlying the lower pad structure and having a different material composition than the lower pad structure. The conductive contact structures extend through the composite pad structures and to the conductive structures of the stack structure. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.
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公开(公告)号：US12250812B2
公开(公告)日：2025-03-11
申请号：US18094906
申请日：2023-01-09
Applicant: Micron Technology, Inc.
Inventor： Jordan D. Greenlee , Nancy M. Lomeli , John D. Hopkins , Jiewei Chen , Indra V. Chary , Jun Fang , Vladimir Samara , Kaiming Luo , Rita J. Klein , Xiao Li , Vinayak Shamanna
Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号：US12225721B2
公开(公告)日：2025-02-11
申请号：US17841925
申请日：2022-06-16
Applicant: Micron Technology, Inc.
Inventor： John D. Hopkins , Nancy M. Lomeli
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. A stack comprising vertically-alternating first tiers and second tiers is formed above the conductor tier. The stack comprises laterally-spaced memory-block regions. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. Spaced insulator-material bodies are formed in and longitudinally-along opposing sides of individual of the memory-block regions in a lowest of the first tiers. After forming the spaced insulator-material bodies, conductive material is formed in the lowest first tier that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.
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公开(公告)号：US12213311B2
公开(公告)日：2025-01-28
申请号：US17670685
申请日：2022-02-14
Applicant: Micron Technology, Inc.
Inventor： John D. Hopkins , Alyssa N. Scarbrough
Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a lower portion of a stack that will comprise vertically-alternating first tiers and second tiers on a substrate. The stack comprises laterally-spaced memory-block regions, Material of the first tiers is of different composition from material of the second tiers. Horizontally-elongated lines are formed in the lower portion that are individually between immediately-laterally-adjacent of the memory-block regions. The lines comprise sacrificial material. The lines individually comprise laterally-opposing projections longitudinally therealong in a lowest of the first tiers. The vertically-alternating first tiers and second tiers of an upper portion of the stack are formed above the lower portion and the lines, and channel-material strings are formed that extend through the first tiers and the second tiers in the upper portion to the lower portion. Horizontally-elongated trenches are formed into the stack that are individually between the immediately-laterally-adjacent memory-block regions and extend to the line there-between. The sacrificial material of the lines and projections is removed through the trenches. Intervening material is formed in the trenches and void-spaces left as a result of the removing of the sacrificial material of the lines. Other embodiments are disclosed.
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公开(公告)号：US12176034B2
公开(公告)日：2024-12-24
申请号：US17583472
申请日：2022-01-25
Applicant: Micron Technology, Inc.
Inventor： Alyssa N. Scarbrough , M. Jared Barclay , John D. Hopkins
IPC: H01L29/76 , G11C16/04 , H01L23/522 , H01L23/528 , H10B41/10 , H10B41/27 , H10B43/10 , H10B43/27
Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. A through-array-via (TAV) region comprises TAVs that individually extend through a lowest of the conductive tiers. Insulative rings are in the lowest conductive tier in the TAV region. Individual of the insulative rings encircle individual of the TAVs. The insulative rings extend through the lowest conductive tier and into the conductor tier. Outer rings are in the lowest conductive tier that individually encircle one of the individual insulative rings that encircle the individual TAVs. Other embodiments, including method, are disclosed.
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Patent Agency Ranking
公开(公告)号：US20240251556A1
公开(公告)日：2024-07-25
申请号：US18597695
申请日：2024-03-06
Applicant: Micron Technology, Inc.
Inventor： John D. Hopkins , Nancy M. Lomeli
IPC: H10B43/27 , H01L21/225 , H10B41/27
CPC classification number: H10B43/27 , H01L21/2254 , H10B41/27
Abstract: A liner is formed laterally-outside of individual channel-material strings in one of first tiers and in one of second tiers. The liners are isotropically etched to form void-spaces in the one second tier above the one first tier. Individual of the void-spaces are laterally-between the individual channel-material strings and the second-tier material in the one second tier. Conductively-doped semiconductive material is formed against sidewalls of the channel material of the channel-material strings in the one first tier and that extends upwardly into the void-spaces in the one second tier. The conductively-doped semiconductive material is heated to diffuse conductivity-increasing dopants therein from the void-spaces laterally into the channel material laterally there-adjacent and upwardly into the channel material that is above the void-spaces.
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公开(公告)号：US20240251555A1
公开(公告)日：2024-07-25
申请号：US18585372
申请日：2024-02-23
Applicant: Micron Technology, Inc.
Inventor： Alyssa N. Scarbrough , John D. Hopkins , Jordan D. Greenlee
Abstract: Some embodiments include an integrated assembly having a first memory region, a second memory region offset from the first memory region, and an intermediate region between the first and second memory regions. Channel-material-pillars are arranged within the memory regions. Conductive posts are arranged within the intermediate region. A panel extends across the memory regions and the intermediate region. The panel is laterally between a first memory-block-region and a second memory-block-region. Doped-semiconductor-material is within the memory regions and the intermediate region, and is directly adjacent to the panel. The doped-semiconductor-material is at least part of conductive source structures within the memory regions. Insulative rings laterally surround lower regions of the conductive posts and are between the conductive posts and the doped-semiconductor-material. Insulative liners are along upper regions of the conductive posts. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号：US12040223B2
公开(公告)日：2024-07-16
申请号：US17141722
申请日：2021-01-05
Applicant: Micron Technology, Inc.
Inventor： Darwin A. Clampitt , John D. Hopkins , Madison D. Drake
IPC: H01L21/768 , H01L23/532 , H01L23/535 , H10B41/27 , H10B43/27
CPC classification number: H01L21/7682 , H01L21/76805 , H01L21/76895 , H01L23/53257 , H01L23/5329 , H01L23/535 , H10B41/27 , H10B43/27
Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, strings of memory cells vertically extending through the stack structure, the strings of memory cells individually comprising a channel material vertically extending through the stack structure, a conductive contact structure vertically overlying and in electrical communication with the channel material of a string of memory cells of the strings of memory cells, and a void laterally neighboring the conductive contact structure, the conductive contact structure separated from a laterally neighboring conductive contact structure by the void, a dielectric material, and an additional void laterally neighboring the laterally neighboring conductive contact structure. Related memory devices, electronic systems, and methods are also described.
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公开(公告)号：US12010847B2
公开(公告)日：2024-06-11
申请号：US17691993
申请日：2022-03-10
Applicant: Micron Technology, Inc.
Inventor： Darwin A. Clampitt , Matthew J. King , John D. Hopkins , M. Jared Barclay
CPC classification number: H10B43/27 , H01L23/481 , H01L23/528 , H10B41/10 , H10B41/27 , H10B41/40 , H10B43/10 , H10B43/40
Abstract: Some embodiments include an integrated assembly having a base (e.g., a monocrystalline silicon wafer), and having memory cells over the base and along channel-material-pillars. A conductive structure is between the memory cells and the base. The channel-material-pillars are coupled with the conductive structure. A foundational structure extends into the base and projects upwardly to a level above the conductive structure. The foundational structure locks the conductive structure to the base to provide foundational support to the conductive structure.
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公开(公告)号：US20240160288A1
公开(公告)日：2024-05-16
申请号：US18498422
申请日：2023-10-31
Applicant: Micron Technology, Inc.
Inventor： John D. Hopkins , Mohad Baboli
Abstract: Methods, systems, and apparatus for neuronal to memory device communication are described. An apparatus can include a memory device and a processing device communicatively coupled to the memory device. The processing device can receive neuronal map data associated with at least one image, determine that the neuronal map data is associated with the at least one image, and display the at least one image in response to the determination.
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