公开(公告)号：US12147702B2

公开(公告)日：2024-11-19

申请号：US17579995

申请日：2022-01-20

Applicant: Micron Technology, Inc.

Inventor： Nicolas Soberanes ,  Ezra E. Hartz ,  Jonathan S. Parry ,  Bruce J. Ford ,  Joseph A. De La Cerda ,  Benjamin Rivera

IPC: G06F3/06 ,  G06F12/0811 ,  G06F18/214

Abstract: A host can determine whether to train an AI accelerator of a memory sub-system. Responsive to determining to train the AI accelerator, the host can determine a training category corresponding to a memory access request. The host can also provide an indication to the memory sub-system that causes training of the AI accelerator to be performed based on the training category.

公开(公告)号：US12124322B2

公开(公告)日：2024-10-22

申请号：US17518170

申请日：2021-11-03

Applicant: Micron Technology, Inc.

Inventor： Qing Liang ,  Jonathan S. Parry ,  Giuseppe Cariello ,  Deping He

IPC: G06F11/00 ,  G06F11/07 ,  G06F11/30

CPC classification number: G06F11/073 ,  G06F11/0757 ,  G06F11/076 ,  G06F11/0772 ,  G06F11/3037

Abstract: Techniques for access operation status signaling for memory systems are described. In some examples, a memory system may respond to access commands from a host system by performing access operations such as read or write operations. In accordance with examples as disclosed herein, a system may be configured to support access operation status signaling between a host system and a memory system, which may improve the ability of the system to adapt to various access scenarios, including when access operation completion is delayed. For example, when a memory system is performing an error recovery or media management operation, the memory system may indicate that the error recovery or media management operation is being performed or is otherwise ongoing. Such status signaling may indicate that the memory system is actively performing operations, which may be used to inhibit a reset or reinitialization by a host system.

公开(公告)号：US12105967B2

公开(公告)日：2024-10-01

申请号：US17894794

申请日：2022-08-24

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Robert Loren O. Ursua ,  Sead Zildzic ,  Eric N. Lee ,  Jonathan S. Parry ,  Lakshmi Kalpana K. Vakati ,  Jeffrey S. McNeil

IPC: G06F3/06

CPC classification number: G06F3/0629 ,  G06F3/0625 ,  G06F3/0679

Abstract: A system can include a processing device operatively coupled with the one or more memory devices, to perform operations that include writing data to the one or more memory devices and performing one or more scan operations on a management unit containing the data to determine a current value of a chosen data state metric. Each scan operation can be performed using a corresponding predetermined read-time parameter value. The operations can include determining whether the current value of the chosen data state metric satisfies a criterion, and can also include, responsive to determining that the current value of the chosen data state metric satisfies the criterion, selecting a remedial operation by determining whether redundancy metadata is included in a fault tolerant data stripe on the one or more memory devices. The operations can also include performing the remedial operation with respect to the management unit.

公开(公告)号：US12079481B2

公开(公告)日：2024-09-03

申请号：US17898333

申请日：2022-08-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Chun Sum Yeung ,  Deping He ,  Ting Luo ,  Guang Hu ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0653 ,  G06F3/0679

Abstract: Described are systems and methods related to a memory block erase protocol. An example system includes a memory device having a memory array including a plurality of memory cells. The system further includes a processing device coupled to the memory device. The processing device is to determine a value of a metric associated with the memory array. Responsive to determine that the value of the metric is below a predetermined threshold, the processing device is further to initiate an erase protocol of the memory device. The processing device is further to erase sets of memory cells associated with one or more memory blocks of the memory array. The processing device is further to receive a programming command directed to the first set of memory cells. The processing device is further to perform a programming operation with respect to a set of memory cells responsive to receiving the programming command.

公开(公告)号：US12050773B2

公开(公告)日：2024-07-30

申请号：US17400942

申请日：2021-08-12

Applicant: Micron Technology, Inc.

Inventor： Giuseppe Cariello ,  Jonathan S. Parry

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/061 ,  G06F3/0655 ,  G06F3/0679

Abstract: Methods, systems, and devices for using a completion flag for memory operations are described. A completion flag for a memory device may indicate whether at least one access operation has been completed at the memory device. A controller may poll the completion flag, and if the completion flag indicates that at least one access operation has been completed at the memory device, the controller may poll a status register for the memory device to obtain additional information regarding one or more completed access operations at the memory device.

公开(公告)号：US12001358B2

公开(公告)日：2024-06-04

申请号：US18114617

申请日：2023-02-27

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Jonathan S. Parry

IPC: G06F13/16 ,  G06F1/12

CPC classification number: G06F13/1689 ,  G06F1/12

Abstract: Methods, systems, and devices for status check using signaling are described. A memory system may receive ready signals from memory dies. The ready signal may indicate whether a memory die is available to receive a command. The memory system may generate an indicator of whether the memory die is available based on values of ready signals. The memory system may output the indicator to a controller over one or more pins based on generating the indicator.

公开(公告)号：US20240078020A1

公开(公告)日：2024-03-07

申请号：US17929962

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Jonathan S. Parry ,  Yanhua Bi

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0652 ,  G06F3/0659 ,  G06F3/0688

Abstract: Methods, systems, and devices for write booster pinning are described. In some examples, a memory device may receive one or more commands (e.g., write commands) while operating in a first mode (e.g., a write booster mode). Some write commands may include an indication to pin the data to one or more SLCs. For example, a first write command may be associated with first data and a first indicator and a second write command may be associated with second data. Both the first data and the second data may be written to one or more SLCs. When maintenance operations are performed on the SLCs, the second data may be moved (e.g., written) to one or more MLCs. Additionally or alternatively, the memory system may receive one or more commands to unpin data (e.g., the first data) such that it may be moved to one or more MLCs during subsequent maintenance operations.

公开(公告)号：US20240053905A1

公开(公告)日：2024-02-15

申请号：US17888309

申请日：2022-08-15

Applicant: Micron Technology, Inc.

Inventor： Reshmi Basu ,  Jonathan S. Parry ,  Giuseppe Cariello ,  Stephen Hanna

IPC: G06F3/06

CPC classification number: G06F3/0631 ,  G06F3/0659 ,  G06F3/0683 ,  G06F3/0604

Abstract: Methods, systems, and devices for compression and decompression of trim data are described. A memory system may store one or more trim settings to a volatile memory in a compressed manner, and may expand (e.g., decompress) the data as part of a write operation to a non-volatile memory (e.g., during a start-up procedure). For example, compressed (e.g., non-expanded) data including trim settings may be stored to a volatile memory, and a portion of the array of volatile memory cells may be temporarily allocated to expand the data (e.g., copy the data, invert the data, copy the inverted data). Once the data is expanded, it may be stored in the non-volatile memory, and the temporarily allocated portion of the array of volatile memory cells may be reallocated (e.g., allocated for another purpose). The expanded data may include multiple copies and inverted copies of the trim settings.

公开(公告)号：US11868632B2

公开(公告)日：2024-01-09

申请号：US17736605

申请日：2022-05-04

Applicant: Micron Technology, Inc.

Inventor： David Aaron Palmer ,  Jonathan S. Parry

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0632 ,  G06F3/0625 ,  G06F3/0679

Abstract: Methods, systems, and devices for power control for boot-up of memory systems are described. A memory system may be configured to boot-up using two different power modes: a lower-power mode, and a higher-power mode. The memory system may perform a series of evaluations to determine whether the memory system is to switch to the lower-power mode during boot-up operations, or stay in the higher-power mode. For example, the memory system may check one or more of: a history of previous boot-up failures, a voltage of an associated power management integrated circuit, a history of asynchronous power loss at the device, a power-mode configuration of the host device, or a history of host-initiated power-down commands. In some examples, by switching to the lower-power mode, the memory system may avoid repeatedly failing multiple boot-up cycles and may instead successfully boot-up the memory system.

公开(公告)号：US20230359551A1

公开(公告)日：2023-11-09

申请号：US17633523

申请日：2021-03-19

Applicant: Micron Technology, Inc.

Inventor： Xu Zhang ,  Jonathan S. Parry ,  Zhen Gu

IPC: G06F12/0882 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0246 ,  G06F12/0882 ,  G06F13/1668

Abstract: Methods, systems, and devices for techniques for a fragment cursor are described. A memory system may receive one or more write commands, each write command corresponding to a data fragment. The memory device may store the data fragments to a cursor (e.g., a fragment cursor) in a cache upon receiving the write commands, the cursor configured to store data fragments with a size less than a fragment size threshold (e.g., a page). The memory system may detect a memory management operation (e.g., power down, cache synchronization, data relocation, etc.) and write the cached data fragments to a block of memory cells of a memory device using the cursor. In some examples, the cursor may have a different associated mapping unit than other cursors of the memory system.