公开(公告)号：US10943794B2

公开(公告)日：2021-03-09

申请号：US16513466

申请日：2019-07-16

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Akshay N. Singh ,  Kyle K. Kirby

IPC: H01L21/48 ,  H01L23/48 ,  H01L21/66 ,  H01L23/498 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.

公开(公告)号：US20210035917A1

公开(公告)日：2021-02-04

申请号：US16524989

申请日：2019-07-29

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Dong Soon Lim ,  Randon K. Richards ,  Aparna U. Limaye

IPC: H01L23/552 ,  H01L23/66 ,  H01Q1/22 ,  H01L23/31 ,  H01L21/56

Abstract: Semiconductor devices with antennas and electromagnetic interference (EMI) shielding, and associated systems and methods, are described herein. In one embodiment, a semiconductor device includes a semiconductor die coupled to a package substrate. An antenna structure is disposed over and/or adjacent the semiconductor die. An electromagnetic interference (EMI) shield is disposed between the semiconductor die and the antenna structure to shield at least the semiconductor die from electromagnetic radiation generated by the antenna structure and/or to shield the antenna structure from interference generated by the semiconductor die. A first dielectric material and/or a thermal interface material can be positioned between the semiconductor die and the EMI shield, and a second dielectric material can be positioned between the EMI shield and the antenna structure. In some embodiments, the semiconductor device includes a package molding over at least a portion of the antenna, the EMI shield, and/or the second dielectric material.

公开(公告)号：US20210005526A1

公开(公告)日：2021-01-07

申请号：US16503363

申请日：2019-07-03

Applicant: Micron Technology, Inc.

Inventor： Chan H. Yoo ,  Owen R. Fay

IPC: H01L23/36 ,  H05K7/20 ,  H01L23/42 ,  H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00

Abstract: Semiconductor assemblies including thermal management configurations for reducing heat transfer between vertically stacked devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor assemblies comprise at least one memory device mounted over a logic device with a thermally conductive layer, a thermal-insulator interposer, or a combination thereof disposed between the memory device and the logic device. The thermally conductive layer includes a structure configured to transfer the thermal energy across a horizontal plane. The thermal-insulator interposer includes a structure configured to reduce heat transfer between the logic device and the memory device.

公开(公告)号：US10790251B2

公开(公告)日：2020-09-29

申请号：US16013237

申请日：2018-06-20

Applicant: Micron Technology, Inc.

Inventor： Christopher J. Gambee ,  Nhi Doan ,  Chandra S. Tiwari ,  Owen R. Fay ,  Ying Chen

IPC: H01L23/00 ,  H01L21/027 ,  H01L21/56

Abstract: Methods of forming supports for 3D structures on semiconductor structures comprise forming the supports from photodefinable materials by deposition, selective exposure and curing. Semiconductor dice including 3D structures having associated supports, and semiconductor devices are also disclosed.

公开(公告)号：US10763186B2

公开(公告)日：2020-09-01

申请号：US16237111

申请日：2018-12-31

Applicant: Micron Technology, Inc.

Inventor： Andrew M. Bayless ,  Wayne H. Huang ,  Owen R. Fay

IPC: H01L23/31 ,  H01L23/473 ,  H01L21/56 ,  H01L23/36 ,  H01L23/467

Abstract: A semiconductor device assembly can include a first die package comprising a bottom side; a top side; and lateral sides extending between the top and bottom sides. The assembly can include an encapsulant material encapsulating the first die package. In some embodiments, the assembly includes a cooling cavity in the encapsulant material. The cooling cavity can have a first opening; a second opening; and an elongate channel extending from the first opening to the second opening. In some embodiments, the elongate channel surrounds at least two of the lateral sides of the first die package. In some embodiments, the elongate channel is configured to accommodate a cooling fluid.

公开(公告)号：US10741460B2

公开(公告)日：2020-08-11

申请号：US16162195

申请日：2018-10-16

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Kyle K. Kirby ,  Luke G. England ,  Jaspreet S. Gandhi

IPC: H01L21/66 ,  H01L23/00

Abstract: An interconnect assembly includes a bond pad and an interconnect structure configured to electrically couple an electronic structure to the bond pad. The interconnect structure physically contacts areas of the bond pad that are located outside of a probe contact area that may have been damaged during testing. Insulating material covers the probe contact area and defines openings spaced apart from the probe contact area. The interconnect structure extends through the openings to contact the bond pad.

公开(公告)号：US20200211993A1

公开(公告)日：2020-07-02

申请号：US16236237

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Suresh Yeruva ,  Owen R. Fay ,  Sameer S. Vadhavkar ,  Adriel Jebin Jacob Jebaraj ,  Wayne H. Huang

IPC: H01L23/00

Abstract: A method of manufacturing a semiconductor device having a conductive substrate having a first surface, a second surface opposite the first surface, and a passivation material covering a portion of the first surface can include applying a seed layer of conductive material to the first surface of the conductive substrate and to the passivation material, the seed layer having a first face opposite the conductive substrate. The method can include forming a plurality of pillars comprising layers of first and second materials. The method can include etching the seed layer to undercut the seed layer between the conductive substrate and the first material of at least one of the pillars. In some embodiments, a cross-sectional area of the seed layer in contact with the passivation material between the first material and the conductive substrate is less than the cross-sectional area of the second material.

公开(公告)号：US20200075384A1

公开(公告)日：2020-03-05

申请号：US16119414

申请日：2018-08-31

Applicant: Micron Technology, Inc.

Inventor： Shijian Luo ,  Owen R. Fay

IPC: H01L21/683

Abstract: A semiconductor device assembly that includes a semiconductor device having a first side and a second side connected to a substrate. A layer of self-depolymerizing polymer connects the semiconductor device to the substrate. The layer of self-depolymerizing layer is positioned between the first side of the semiconductor device and the substrate. The layer of self-depolymerizing polymer is configured to selectively release the substrate from the semiconductor device. The layer of self-depolymerizing polymer selectively depolymerizes to release the substrate. The substrate enables processing to occur on the second side of the semiconductor device. A material may be applied to a portion of the layer of self-depolymerizing polymer causing the entire layer to depolymerize and release the substrate from the semiconductor device. Energy may be applied to a portion of the layer of self-depolymerizing polymer causing the entire layer to depolymerize and release the substrate from the semiconductor device.

公开(公告)号：US20190341270A1

公开(公告)日：2019-11-07

申请号：US16513466

申请日：2019-07-16

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Akshay N. Singh ,  Kyle K. Kirby

IPC: H01L21/48 ,  H01L25/065 ,  H01L21/66 ,  H01L23/498 ,  H01L23/48

Abstract: A semiconductor device assembly and method of forming a semiconductor device assembly that includes a first substrate, a second substrate disposed over the first substrate, at least one interconnect between the substrates, and at least one pillar extending from the bottom surface of the first substrate. The pillar is electrically connected to the interconnect and is located adjacent to a side of the first substrate. The pillar is formed by filling a via through the substrate with a conductive material. The first substrate may include an array of pillars extending from the bottom surface adjacent to a side of the substrate that are formed from a plurality of filled vias. The substrate may include a test pad located on the bottom surface or located on the top surface. The pillars may include a removable coating enabling the pillars to be probed without damaging the inner conductive portion of the pillar.

公开(公告)号：US10418330B2

公开(公告)日：2019-09-17

申请号：US14253504

申请日：2014-04-15

Applicant: Micron Technology, Inc.

Inventor： Owen R. Fay ,  Steven R. Smith

IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/31

Abstract: Semiconductor devices may include a substrate and a semiconductor die on the substrate. The semiconductor die may include an active surface and a lateral edge at a periphery of the active surface. An electrically insulating material may be located on the active surface proximate the lateral edge. The electrically insulating material may be distinct from any other material located on the active surface. A wire bond may extend from the active surface, over the electrically insulating material, to the substrate. Methods of making semiconductor devices may involve positioning an electrically insulating material on an active surface of a semiconductor die proximate a lateral edge at a periphery of an active surface. After positioning the electrically insulating material on the active surface, a wire bond extending from the active surface, over the electrically insulating material, to the substrate may be formed.