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    Methods used in forming an array of elevationally-extending transistors
    81.
    发明授权
    Methods used in forming an array of elevationally-extending transistors 有权

    公开(公告)号：US10361216B2

    公开(公告)日：2019-07-23

    申请号：US15710432

    申请日：2017-09-20

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  E. Allen McTeer

    IPC: H01L27/11582 ,  H01L27/11556

    Abstract: A method used in forming an array of elevationally-extending transistors comprises forming vertically-alternating tiers of insulating material and void space. Such method includes forming (a) individual longitudinally-aligned channel openings extending elevationally through the insulating-material tiers, and (b) horizontally-elongated trenches extending elevationally through the insulating-material tiers. The void-space tiers are filled with conductive material by flowing the conductive material or one or more precursors thereof through at least one of (a) and (b) to into the void-space tiers. After the filling, transistor channel material is formed in the individual channel openings along the insulating-material tiers and along the conductive material in the filled void-space tiers.

    Assemblies having vertically-stacked conductive structures
    83.
    发明授权
    Assemblies having vertically-stacked conductive structures 有权

    公开(公告)号：US10170493B1

    公开(公告)日：2019-01-01

    申请号：US15848398

    申请日：2017-12-20

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  Everett A. McTeer

    IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/285 ,  H01L27/11565 ,  H01L27/11519

    Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.

    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
    84.
    发明授权
    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US12300318B2

    公开(公告)日：2025-05-13

    申请号：US17727515

    申请日：2022-04-22

    Applicant: Micron Technology, Inc.

    Inventor： Alyssa N. Scarbrough ,  Jordan D. Greenlee ,  John D. Hopkins

    IPC: H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27

    Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers directly above a conductor tier. Strings of memory cells comprise channel-material strings that extend through the insulative tiers and the conductive tiers. The channel-material strings directly electrically couple to conductor material of the conductor tier. Below the stack, an insulating tier is directly above the conductor tier and a metal-material tier is directly above the insulating tier. Conductive rings extend through the metal-material tier and the insulating tier to conductor material of the conductor tier. The conductive rings individually are around individual horizontal locations directly above which are individual of the channel-material strings. The channel-material strings directly electrically couple to the conductor material of the conductor tier through the insulating tier by the conductive rings. Other embodiments, including method, are disclosed.

    HEAT TRANSFER SYSTEM CONTROLLER AND METHOD
    86.
    发明申请
    HEAT TRANSFER SYSTEM CONTROLLER AND METHOD 有权

    公开(公告)号：US20250071940A1

    公开(公告)日：2025-02-27

    申请号：US18773959

    申请日：2024-07-16

    Applicant: Micron Technology, Inc.

    Inventor： John Hopkins ,  Jordan D. Greenlee

    IPC: H05K7/20 ,  H01L21/67

    Abstract: Apparatus and methods are disclosed, including cooling devices and systems. Cooling devices and methods are shown that include dissolved ions in cooling fluid, such as cooling water. Cooling devices and methods are shown that include an electrical conductivity measurement sensor within the cooling water, wherein the electrical conductivity measurement sensor includes an electrode resistant to the dissolved ions.

    Methods of Filling Openings with Conductive Material, and Assemblies Having Vertically-Stacked Conductive Structures
    88.
    发明申请
    Methods of Filling Openings with Conductive Material, and Assemblies Having Vertically-Stacked Conductive Structures 有权

    公开(公告)号：US20240407160A1

    公开(公告)日：2024-12-05

    申请号：US18798634

    申请日：2024-08-08

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  John Mark Meldrim ,  Everett A McTeer

    IPC: H10B41/27 ,  H01L21/285 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

    Abstract: Some embodiments include a method in which an assembly is formed to have voids within a stack, and to have slits adjacent the voids. Peripheral boundaries of the voids have proximal regions near the slits and distal regions adjacent the proximal regions. A material is deposited within the voids under conditions which cause the material to form to a greater thickness along the distal regions than along the proximal regions. Some embodiments include an assembly having a stack of alternating first and second levels. The second levels include conductive material. Panel structures extend through the stack. The conductive material within the second levels has outer edges with proximal regions near the panel structures and distal regions adjacent the proximal regions. Interface material is along the outer edges of the conductive material and has a different composition along the proximal regions than along the distal regions.

    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells
    89.
    发明授权
    Memory arrays comprising strings of memory cells and methods used in forming a memory array comprising strings of memory cells 有权

    公开(公告)号：US12159674B2

    公开(公告)日：2024-12-03

    申请号：US17409476

    申请日：2021-08-23

    Applicant: Micron Technology, Inc.

    Inventor： Jordan D. Greenlee ,  John D. Hopkins ,  M. Jared Barclay ,  Andrew Li ,  Aireus Christensen

    IPC: H10B43/27 ,  G11C16/04 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

    Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed that individually comprise a vertical stack comprising alternating first tiers and second tiers are formed directly above the conductor tier. Material of the first tiers is sacrificial and of different composition from material of the first tiers. Channel-material strings extend through the first tiers and the second tiers. Conducting material in a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. A horizontally-elongated trench is formed between immediately-laterally-adjacent of the memory-block regions. The trenches extend downwardly into the conducting material. After forming the trenches, lateral-sidewall regions of the conducting material that are aside the individual trenches in the lowest first tier is doped with an impurity. The sacrificial material is etched from the first tiers through the trenches selectively relative to the doped lateral-sidewall regions of the conducting material. Other embodiments, including structure, are disclosed.

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