公开(公告)号：US20210257298A1

公开(公告)日：2021-08-19

申请号：US16790148

申请日：2020-02-13

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Jian Li ,  Graham R. Wolstenholme ,  Paolo Tessariol ,  George Matamis ,  Nancy M. Lomeli

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768

Abstract: Microelectronic devices include stadium structures within a stack structure and substantially symmetrically distributed between a first pillar structure and a second pillar structure, each of which vertically extends through the stack structure. The stack structure includes a vertically alternating sequence of insulative materials and conductive materials arranged in tiers. Each of the stadium structures includes staircase structures having steps including lateral ends of some of the tiers. The substantially symmetrical distribution of the stadium structures, and fill material adjacent such structures, may substantially balance material stresses to avoid or minimize bending of the adjacent pillars. Related methods and systems are also disclosed.

公开(公告)号：US12219757B2

公开(公告)日：2025-02-04

申请号：US17836357

申请日：2022-06-09

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material-string structures of memory cells extend through the insulative tiers and the conductive tiers. The channel-material-string structures individually comprise an upper portion above and joined with a lower portion. Individual of the channel-material-string structures comprise at least one external jog surface in a vertical cross-section where the upper and lower portions join. Other embodiments, including method are disclosed.

公开(公告)号：US20250017007A1

公开(公告)日：2025-01-09

申请号：US18347752

申请日：2023-07-06

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Indra V. Chary ,  Nancy M. Lomeli ,  Xiao Li

IPC: H10B43/27 ,  H01L21/768 ,  H10B43/10 ,  H10B43/35

Abstract: A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure comprising insulative structures and electrically conductive structures vertically alternating with the insulative structures, pillar structures extending vertically through the stack structure, an etch stop material vertically overlaying the stack structure, and a first dielectric material vertically overlying the etch stop material. The method further includes removing portions of the first dielectric material, the etch stop material, and an upper region of the stack structure to form a trench interposed between horizontally neighboring groups of the pillar structures, forming a liner material within the trench, and substantially filling a remaining portion of the trench with a second dielectric material to form a dielectric barrier structure.

公开(公告)号：US12041769B2

公开(公告)日：2024-07-16

申请号：US18047245

申请日：2022-10-17

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee ,  Nancy M. Lomeli

IPC: H10B43/50 ,  G11C5/02 ,  G11C5/06 ,  H01L23/538 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L23/5386 ,  H10B43/27 ,  H10B43/50

Abstract: A method of forming a microelectronic device comprises forming a sacrificial material over a base structure. Portions of the sacrificial material are replaced with an etch-resistant material. A stack structure is formed over the etch-resistant material and remaining portions of the sacrificial material. The stack structure comprises a vertically alternating sequence of insulative material and additional sacrificial material arranged in tiers, and at least one staircase structure horizontally overlapping the etch-resistant material and having steps comprising horizontal ends of the tiers. Slots are formed to vertically extend through the stack structure and the remaining portions of the sacrificial material. The sacrificial material and the additional sacrificial material are selectively replaced with conductive material after forming the slots to respectively form lateral contact structures and conductive structures. Microelectronic devices, memory devices, and electronic systems are also described.

公开(公告)号：US11956950B2

公开(公告)日：2024-04-09

申请号：US18080382

申请日：2022-12-13

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Nancy M. Lomeli

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H01L21/768 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L21/76838 ,  H10B43/27

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The conductive tiers comprise metal along sides of the memory blocks. Silicon is formed between the memory blocks over the metal of the conductive tiers. The silicon and the metal react to form metal silicide therefrom that is directly against and longitudinally-along the metal of individual of the conductive tiers. After the reacting, unreacted of the silicon is removed from between the memory blocks and intervening material is formed between and longitudinally-along the memory blocks. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20240088031A1

公开(公告)日：2024-03-14

申请号：US17930656

申请日：2022-09-08

Applicant: Micron Technology, Inc.

Inventor： Lifang Xu ,  Bo Zhao ,  Jeffrey D. Runia ,  Nancy M. Lomeli

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/535

CPC classification number: H01L23/5283 ,  H01L21/76816 ,  H01L21/76895 ,  H01L23/535

Abstract: A microelectronic device includes a stack structure including a block region and a non-block region. The block region includes blocks separated from one another in a first horizontal direction by insulative slot structures and each including a vertically alternating sequence of conductive material and insulative material arranged in tiers. At least one of the blocks has stadium structures individually including staircase structures having steps comprising edges of some of the tiers. The non-block region neighbors the block region in the first horizontal direction. The non-block region includes additional stadium structures individually terminating at a relatively higher vertical position within the stack structure than at least one of the stadium structures at least partially within boundaries thereof in a second horizontal direction orthogonal to the first horizontal direction. Related memory devices, electronic systems, and methods are also described.

公开(公告)号：US11917817B2

公开(公告)日：2024-02-27

申请号：US17125200

申请日：2020-12-17

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  John D. Hopkins ,  Lifang Xu ,  Nancy M. Lomeli ,  Indra V. Chary ,  Kar Wui Thong ,  Shicong Wang

IPC: H10B43/50 ,  H10B41/27 ,  H01L21/768 ,  G11C5/02 ,  G11C5/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H01L21/768 ,  H10B43/27

Abstract: A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive material and insulative material arranged in tiers. The stack structure has blocks separated from one another by first dielectric slot structures. Each of the blocks comprises two crest regions, a stadium structure interposed between the two crest regions in a first horizontal direction and comprising opposing staircase structures each having steps comprising edges of the tiers of the stack structure, and two bridge regions neighboring opposing sides of the stadium structure in a second horizontal direction orthogonal to the first horizontal direction and having upper surfaces substantially coplanar with upper surfaces of the two crest regions. At least one second dielectric slot structure is within horizontal boundaries of the stadium structure in the first horizontal direction and partially vertically extends through and segmenting each of the two bridge regions. Memory devices, electronic systems, and methods of forming microelectronic devices are also described.

公开(公告)号：US20230290721A1

公开(公告)日：2023-09-14

申请号：US17689527

申请日：2022-03-08

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Jiewei Chen ,  Sijia Yu ,  Chieh Hsien Quek ,  Rita J. Klein ,  Nancy M. Lomeli

IPC: H01L23/522 ,  H01L23/532 ,  H01L27/11556 ,  H01L27/11582

CPC classification number: H01L23/5226 ,  H01L23/53257 ,  H01L23/53271 ,  H01L23/5329 ,  H01L27/11556 ,  H01L27/11582

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Individual of the conductive tiers comprise laterally-outer edges comprising conductive molybdenum-containing metal material extending horizontally-along its memory block. Channel-material strings extend through the insulative tiers and the conductive tiers. At least one of conductive or semiconductive material is formed extending horizontally-along the memory blocks laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material that extends horizontally-along its memory block. Insulator material extending horizontally-along the memory blocks is formed laterally-outward of the at least one of the conductive or the semiconductive material that is laterally-outward of the laterally-outer edges comprising the conductive molybdenum-containing metal material. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US11744072B2

公开(公告)日：2023-08-29

申请号：US17391453

申请日：2021-08-02

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Justin B. Dorhout ,  Nirup Bandaru ,  Damir Fazil ,  Nancy M. Lomeli ,  Jivaan Kishore Jhothiraman ,  Purnima Narayanan

IPC: H10B41/10 ,  H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: Some embodiments include an integrated assembly having a first deck which has first memory cells, and having a second deck which has second memory cells. The first memory cells have first control gate regions which include a first conductive material vertically between horizontally-extending bars of a second conductive material. The second memory cells have second control gate regions which include a fourth conductive material along an outer surface of a third conductive material. A pillar passes through the first and second decks. The pillar includes a dielectric-barrier material laterally surrounding a channel material. The first and fourth materials are directly against the dielectric-barrier material. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20230207470A1

公开(公告)日：2023-06-29

申请号：US18057478

申请日：2022-11-21

Applicant: Micron Technology, Inc.

Inventor： Shuangqiang Luo ,  Nancy M. Lomeli

IPC: H01L23/535 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

CPC classification number: H01L23/535 ,  H01L23/5283 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11582

Abstract: A microelectronic device is disclosed, comprising: a stack structure comprising vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, the stack structure having blocks separated from one another by filled slot structures; a source tier structure underlying the stack structure and comprising: a merged conductive structure adjacent a first discrete conductive structure in a first direction; and a second discrete conductive structure in the first direction that is spaced apart from the merged conductive by the first discrete conductive structure; a first support contact structure on the first discrete conductive structure; and a subsequent support contact structure on the merged conductive structure and adjacent the first support contact in the first direction, wherein one of the filled slot structures is vertically directly above at least a portion of the merged conductive structure.