Abstract:
A system and method for recognizing markers on, e.g., a PCB (printed circuit board). In one aspect, a system for recognizing a marker in an image comprises an image capture module (14) for extracting image features associated with an input image of a ROI (region of interest) captured through a lens 15, an image processor (16) comprising a first marker recognition processor (17) for recognizing a marker in the input image based on a normalized correlation and a second marker recognition processor (18) for recognizing a marker in the input image based on gray value histograms; a training module 19 for building template images and histograms that are used by the image processor (16) to detect a marker in the input image and a database (20) for indexing and storing trained template images and trained histograms.
Abstract:
A system and method for modeling binaural shells for hearing aids, wherein the system is configured to load data associated with a first and a second ear shell. The system is further configured to register the data associated with the first and the second ear shells and process the first ear shell. The system is also configured to store data associated with processing the first ear shell and then map the data associated with processing the first ear shell to the second ear shell. Subsequently, the mapped second ear shell is interactively adjusted by an operator to compensate for an inconsistency in the mapped second ear shell.
Abstract:
Methods of forming a microelectronic structure are described. Embodiments of those methods include providing a substrate comprising a first reflective layer disposed on a second reflective layer, wherein the thickness of the first reflective layer and the thickness of the second reflective layer are less than about 100 angstroms, and forming a ruthenium oxide layer on the substrate, wherein the ruthenium oxide layer is about 50 angstroms or less.
Abstract:
Some embodiments for a method to fill interlayer vias with a suitable metal in a ferroelectric polymer memory die to reduce the step height and improve the thermal and electrical properties of the via. The method uses an electroless plating method to fill the vias, which is compatible with the ferroelectric polymer memory die processing temperature limits. The resulting process produces via fill metal plugs in the ferroelectric memory die, which allows for the deposition of a thin metal layer over the vias, while at the same time improving the electrical and thermal properties of the vias. Other embodiments are described and claimed herein.
Abstract:
A system and method for ground glass nodule (GGN) segmentation is provided. The method comprises: selecting a point in a medical image, wherein the point is located in a GGN; defining a volume of interest (VOI) around the point, wherein the VOI comprises the GGN; removing a chest wall from the VOI; obtaining an initial state for a Markov random field; segmenting the VOI, wherein the VOI is segmented using the Markov random field; identifying vessels in the volume of interest; segmenting the vessels; and removing segmented vessels from the segmented ground glass nodule.
Abstract:
The invention provides bumps between a die and a substrate with a height greater than or equal to a height of a waveguide between the die and the substrate. The bumps may be formed on a die prior to that die being singulated from a wafer.
Abstract:
A system and method for ground glass nodule (GGN) segmentation is provided. The method comprises: selecting a point in a medical image, wherein the point is located in a GGN; defining a volume of interest (VOI) around the point, wherein the VOI comprises the GGN; removing a chest wall from the VOI; obtaining an initial state for a Markov random field; and segmenting the VOI, wherein the VOI is segmented using the Markov random field.
Abstract:
A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner silicides with less likelihood of delamination or metal oxidation may thus be formed.
Abstract:
A method for monitoring a slab filler, including grabbing a dispensing frame from a dispensing side of the slab filler, and grabbing a discharge frame from a discharge side of the slab filler. The method further includes classifying a plurality of cavities in the slab filler according to a correlation between the dispensing frame and at least one template, and classifying the plurality of cavities in the slab filler according to a correlation between the discharge frame and the template.
Abstract:
A silicide having variable internal metal concentration tuned to surface conditions at the interface between the silicide and adjoining layers is employed within an integrated circuit. Higher silicon/metal (silicon-rich) ratios are employed near the interfaces to adjoining layers to reduce lattice mismatch with underlying polysilicon or overlying oxide, thereby reducing stress and the likelihood of delamination. A lower silicon/metal ratio is employed within an internal region of the silicide, reducing resistivity. The variable silicon/metal ratio is achieved by controlling reactant gas concentrations or flow rates during deposition of the silicide. Thinner suicides with less likelihood of delamination or metal oxidation may thus be formed.