公开(公告)号：US09678866B1

公开(公告)日：2017-06-13

申请号：US14724827

申请日：2015-05-29

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/46 ,  G06F12/06

CPC classification number: G06F12/063 ,  G06F3/061 ,  G06F3/0656 ,  G06F3/0683 ,  G06F9/3004 ,  G06F9/3836 ,  G06F9/467 ,  G06F2212/251 ,  H04L45/74

Abstract: A transactional memory (TM) includes a control circuit pipeline and an associated memory unit. The memory unit stores a plurality of rings. The pipeline maintains, for each ring, a head pointer and a tail pointer. A ring operation stage of the pipeline maintains the pointers as values are put onto and are taken off the rings. A put command causes the TM to put a value into a ring, provided the ring is not full. A get command causes the TM to take a value off a ring, provided the ring is not empty. A put with low priority command causes the TM to put a value into a ring, provided the ring has at least a predetermined amount of free buffer space. A get from a set of rings command causes the TM to get a value from the highest priority non-empty ring (of a specified set of rings).

公开(公告)号：US09665519B2

公开(公告)日：2017-05-30

申请号：US14591003

申请日：2015-01-07

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4022 ,  G06F13/4027 ,  G06F13/4221

Abstract: In response to receiving a “Return Available PPI Credits” command from a credit-aware (CA) device, a packet engine sends a “Credit To Be Returned” (CTBR) value it maintains for that device back to the CA device, and zeroes out its stored CTBR value. The CA device adds the credits returned to a “Credits Available” value it maintains. The CA device uses the “Credits Available” value to determine whether it can issue a PPI allocation request. The “Return Available PPI Credits” command does not result in any PPI allocation or de-allocation. In another aspect, the CA device issues one PPI allocation request to the packet engine when its recorded “Credits Available” value is zero or negative. If the PPI allocation request cannot be granted, then it is buffered in the packet engine, and is resubmitted within the packet engine, until the packet engine makes the PPI allocation.

公开(公告)号：US09584637B2

公开(公告)日：2017-02-28

申请号：US14184455

申请日：2014-02-19

Applicant: Netronome Systems, Inc.

Inventor： Ron Lamar Swartzentruber ,  Steven W. Zagorianakos ,  Gavin J. Stark

IPC: H04L12/879 ,  H04L29/08 ,  H04L12/801 ,  H04L12/863 ,  H04L29/06 ,  H04L12/861

CPC classification number: H04L69/324 ,  H04L47/34 ,  H04L47/50 ,  H04L49/901 ,  H04L49/9057 ,  H04L69/22

Abstract: Circuitry to provide in-order packet delivery. A packet descriptor including a sequence number is received. It is determined in which of three ranges the sequence number resides. Depending, at least in part, on the range in which the sequence number resides it is determined if the packet descriptor is to be communicated to a scheduler which causes an associated packet to be transmitted. If the sequence number resides in a first “flush” range, all associated packet descriptors are output. If the sequence number resides in a second “send” range, only the received packet descriptor is output. If the sequence number resides in a third “store and reorder” range and the sequence number is the next in-order sequence number the packet descriptor is output; if the sequence number is not the next in-order sequence number the packet descriptor is stored in a buffer and a corresponding valid bit is set.

Abstract translation: 电路提供按顺序分组传送。 接收包括序列号的分组描述符。 确定序列号所在的三个范围中的哪一个。 至少部分地依赖于序列号所在的范围，确定分组描述符是否被传送到导致相关分组被发送的调度器。 如果序列号位于第一个“刷新”范围内，则输出所有关联的数据包描述符。 如果序列号位于第二个“发送”范围内，则仅输出接收到的包描述符。 如果序列号位于第三个“存储和重新排序”范围，并且序列号是下一个顺序序列号，则输出数据包描述符; 如果序列号不是下一个顺序序列号，则分组描述符被存储在缓冲器中并且相应的有效位被置位。

公开(公告)号：US09535851B2

公开(公告)日：2017-01-03

申请号：US14172856

申请日：2014-02-04

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Rolf Neugebauer

IPC: G06F12/10 ,  G06F9/46 ,  G06F13/38

CPC classification number: G06F9/467 ,  G06F12/109 ,  G06F13/385 ,  G06F2212/151 ,  G06F2212/657 ,  G06F2213/0026

Abstract: A transactional memory receives a command, where the command includes an address and a novel DAT (Do Address Translation) bit. If the DAT bit is set and if the transactional memory is enabled to do address translations and if the command is for an access (read or write) of a memory of the transactional memory, then the transactional memory performs an address translation operation on the address of the command. Parameters of the address translation are programmable and are set up before the command is received. In one configuration, certain bits of the incoming address are deleted, and other bits are shifted in bit position, and a base address is ORed in, and a padding bit is added, thereby generating the translated address. The resulting translated address is then used to access the memory of the transactional memory to carry out the command.

Abstract translation: 事务存储器接收命令，其中命令包括地址和小写的DAT（地址转换）位。 如果DAT位被设置，并且事务存储器被使能以进行地址转换，并且如果该命令用于访问（读或写）事务存储器的存储器，则事务存储器对该地址进行地址转换操作 的命令。 地址转换的参数是可编程的，并在接收到命令之前设置。 在一种配置中，输入地址的某些比特被删除，并且其他比特在比特位置被移位，并且基地址被加入，并且添加一个填充比特，从而生成翻译的地址。 然后，所得到的转换地址用于访问事务存储器的存储器以执行命令。

公开(公告)号：US09519484B1

公开(公告)日：2016-12-13

申请号：US14530764

申请日：2014-11-02

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/38

CPC classification number: G06F9/383 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30069 ,  G06F9/30072 ,  G06F9/30145 ,  G06F9/32

Abstract: A multi-processor includes a pool of processors and a common packet buffer memory. Bytes of packet data of a packet are stored in the packet buffer memory. Each processor has an intelligent packet data register file. One processor is tasked with processing the packet, and its packet data register file caches a subset of the bytes. If the register file detects a packet data prefetch trigger condition, and it does not store some of the bytes in a prefetch window, then it prefetches the bytes before such bytes are required in the execution of a subsequent instruction. The processor has instructions that configure the prefetching, that enable such prefetching, and that disable such prefetching in certain ways.

Abstract translation: 多处理器包括处理器池和公共包缓冲存储器。 分组的分组数据的字节存储在分组缓冲存储器中。 每个处理器都有一个智能包数据寄存器文件。 一个处理器的任务是处理分组，并且其分组数据寄存器文件缓存一个字节的子集。 如果寄存器文件检测到分组数据预取触发条件，并且它不在预取窗口中存储一些字节，则在执行后续指令之前需要这些字节之前预取字节。 处理器具有配置预取的指令，这些指令启用这种预取，并且以某些方式禁用这种预取。

公开(公告)号：US09519482B2

公开(公告)日：2016-12-13

申请号：US14311225

申请日：2014-06-20

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30069 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3867

Abstract: A pipelined run-to-completion processor can decode three instructions in three consecutive clock cycles, and can also execute the instructions in three consecutive clock cycles. The first instruction causes the ALU to generate a value which is then loaded due to execution of the first instruction into a register of a register file. The second instruction accesses the register and loads the value into predicate bits in a register file read stage. The predicate bits are loaded in the very next clock cycle following the clock cycle in which the second instruction was decoded. The third instruction is a conditional instruction that uses the values of the predicate bits as a predicate code to determine a predicate function. If a predicate condition (as determined by the predicate function as applied to flags) is true then an instruction operation of the third instruction is carried out, otherwise it is not carried out.

Abstract translation: 流水线运行到完成处理器可以在三个连续的时钟周期中解码三条指令，并且还可以在三个连续的时钟周期内执行指令。 第一条指令使得ALU产生一个值，该值由于执行第一条指令而被加载到寄存器文件的寄存器中。 第二条指令访问寄存器，并将值加载到寄存器文件读取阶段的谓词位。 谓词位在第二条指令被解码的时钟周期之后的下一个时钟周期中被加载。 第三条指令是使用谓词位的值作为谓词代码来确定谓词函数的条件指令。 如果谓词条件（由标记的谓词函数确定）为真，则执行第三条指令的指令操作，否则不执行。

公开(公告)号：US09465651B2

公开(公告)日：2016-10-11

申请号：US14151677

申请日：2014-01-09

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark ,  Steven W. Zagorianakos

IPC: G06F9/46

CPC classification number: G06F9/467

Abstract: A remote processor interacts with a transactional memory that has a memory, local BWC (Byte-Wise Compare) resources, and local NFA (Non-deterministic Finite Automaton) engine resources. The processor causes a byte stream to be transferred into the transactional memory and into the memory. The processor then uses the BWC circuit to find a character signature in the byte stream. The processor obtains information about the character signature from the BWC circuit, and based on the information uses the NFA engine to process the byte stream starting at a byte position determined based at least in part on the results of the BWC circuit. From the time the byte stream is initially written into the transactional memory until the time the NFA engine completes, the byte stream is not read out of the transactional memory.

Abstract translation: 远程处理器与具有内存，本地BWC（Byte-Wise Compare）资源和本地NFA（非确定性有限自动机）引擎资源的事务内存进行交互。 处理器使得字节流被传送到事务存储器并进入存储器。 然后，处理器使用BWC电路在字节流中找到字符签名。 处理器从BWC电路获得关于字符签名的信息，并且基于该信息使用NFA引擎来处理从至少部分基于BWC电路的结果确定的字节位置开始的字节流。 从字节流最初写入事务存储器直到NFA引擎完成时，字节流不会从事务存储器中读出。

公开(公告)号：US09417916B1

公开(公告)日：2016-08-16

申请号：US14530763

申请日：2014-11-02

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F9/46 ,  G06F9/50

CPC classification number: G06F9/3869 ,  G06F9/30043 ,  G06F9/30047 ,  G06F9/30069 ,  G06F9/3012 ,  G06F9/30149 ,  G06F9/32 ,  G06F9/38 ,  G06F9/383 ,  G06F15/76

Abstract: A multi-processor includes a pool of processors and a common packet buffer memory. Bytes of packet data of a packet are stored in the packet buffer memory. Each processor has an intelligent packet data register file. One processor is tasked with processing the packet, and its packet data register file caches a subset of the bytes. Some instructions when executed require that the packet data register file supply the execute stage of the processor with certain bytes of the packet data. The register file detects a packet data prefetch trigger condition, and in response determines if it does not store some of the bytes in a prefetch window. If it does not, then it retrieves those bytes from the packet buffer memory, so that it then has all the bytes in the prefetch window. In one example, a subsequently executed instruction uses the prefetched packet data.

Abstract translation: 多处理器包括处理器池和公共包缓冲存储器。 分组的分组数据的字节存储在分组缓冲存储器中。 每个处理器都有一个智能包数据寄存器文件。 一个处理器的任务是处理分组，并且其分组数据寄存器文件缓存一个字节的子集。 执行时的一些指令要求分组数据寄存器文件以分组数据的特定字节提供处理器的执行级。 寄存器文件检测分组数据预取触发条件，并且响应确定它是否在预取窗口中不存储一些字节。 如果没有，则从包缓冲存储器中检索这些字节，以便它在预取窗口中具有所有字节。 在一个示例中，随后执行的指令使用预取的分组数据。

公开(公告)号：US09348778B2

公开(公告)日：2016-05-24

申请号：US14631748

申请日：2015-02-25

Applicant: Netronome Systems, Inc.

Inventor： Gavin J. Stark

IPC: G06F13/28 ,  G06F17/30 ,  G06F9/34 ,  G06F9/46 ,  G06F13/00 ,  G06F13/42 ,  G06F7/10 ,  G06F12/00

CPC classification number: G06F13/287 ,  G06F7/10 ,  G06F9/34 ,  G06F9/467 ,  G06F12/00 ,  G06F13/00 ,  G06F13/4234 ,  G06F17/30 ,  Y02D10/14 ,  Y02D10/151

Abstract: A transactional memory (TM) receives a lookup command across a bus from a processor. The command includes a memory address, a starting bit position, and a mask size. In response to the command, the TM pulls an input value (IV). The memory address is used to read a word containing multiple result values (RVs) and multiple key values from memory. Each key value indicates a single RV to be output by the TM. A selecting circuit within the TM uses the starting bit position and mask size to select a portion of the IV. The portion of the IV is a key selector value. A key value is selected based upon the key selector value. A RV is selected based upon the key value. The key value is selected by a key selection circuit. The RV is selected by a result value selection circuit.

公开(公告)号：US20160085477A1

公开(公告)日：2016-03-24

申请号：US14492013

申请日：2014-09-20

Applicant: Netronome Systems, Inc.

Inventor： Salma Mirza ,  Gavin J. Stark

IPC: G06F3/06 ,  G06F13/28 ,  G06F12/02

CPC classification number: G06F3/0647 ,  G06F3/0611 ,  G06F3/0656 ,  G06F3/0683 ,  G06F13/28 ,  H04L12/00 ,  H04L12/6418 ,  H04L29/08 ,  H04L47/35 ,  H04L47/624 ,  H04L49/3072 ,  H04L49/9042 ,  H04L69/22

Abstract: An addressless merge command includes an identifier of an item of data, and a reference value, but no address. A first part of the item is stored in a first place. A second part is stored in a second place. To move the first part so that the first and second parts are merged, the command is sent across a bus to a device. The device translates the identifier into a first address ADR1, and uses ADR1 to read the first part. Stored in or with the first part is a second address ADR2 indicating where the second part is stored. The device extracts ADR2, and uses ADR1 and ADR2 to issue bus commands. Each bus command causes a piece of the first part to be moved. When the entire first part has been moved, then device returns the reference value to indicate that the merge command has been completed.

Abstract translation: 无地址合并命令包括数据项的标识符和参考值，但没有地址。 项目的第一部分存储在第一个位置。 第二部分存储在第二部分。 要移动第一部分以使第一部分和第二部分合并，命令通过总线发送到设备。 设备将标识符转换为第一地址ADR1，并使用ADR1读取第一部分。 存储在第一部分中或与第一部分一起存储是指示第二部分被存储在哪里的第二地址ADR2。 该设备提取ADR2，并使用ADR1和ADR2发出总线命令。 每个总线命令使第一部分的一部分被移动。 当整个第一部分被移动时，设备返回参考值以指示合并命令已经完成。