公开(公告)号：US20100210043A1

公开(公告)日：2010-08-19

申请号：US12371724

申请日：2009-02-16

申请人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

发明人： Qizhi Liu ,  Ping-Chuan Wang ,  Kimball M. Watson ,  Zhijian J. Yang

IPC分类号： H01L21/66 ,  G06F19/00

CPC分类号： H01L22/34 ,  H01L2924/3011

摘要： A system, method and device for measuring a depth of a Through-Silicon-Via (TSV) in a semiconductor device region on a wafer during in-line semiconductor fabrication, includes a resistance measurement trench structure having length and width dimensions in a substrate, ohmic contacts on a surface of the substrate disposed on opposite sides of the resistance measurement trench structure, and an unfilled TSV structure in semiconductor device region having an unknown depth. A testing circuit makes contact with the ohmic contacts and measures a resistance therebetween, and a processor connected to the testing circuit calculates a depth of the trench structure and the unfilled TSV structure based on the resistance measurement. The resistance measurement trench structure and the unfilled TSV are created simultaneously during fabrication.

摘要翻译： 在线半导体制造期间，用于测量晶片上的半导体器件区域中的硅硅通孔（TSV）的深度的系统，方法和装置包括在衬底中具有长度和宽度尺寸的电阻测量沟槽结构， 设置在电阻测量沟槽结构的相对侧的衬底的表面上的欧姆接触，以及具有未知深度的半导体器件区域中的未填充的TSV结构。 测试电路与欧姆接触件接触并测量它们之间的电阻，连接到测试电路的处理器基于电阻测量来计算沟槽结构的深度和未填充的TSV结构。 在制造期间同时产生电阻测量沟槽结构和未填充TSV。

公开(公告)号：US07709338B2

公开(公告)日：2010-05-04

申请号：US11614757

申请日：2006-12-21

申请人： Qizhi Liu ,  Peter B. Gray ,  Alvin J. Joseph

发明人： Qizhi Liu ,  Peter B. Gray ,  Alvin J. Joseph

IPC分类号： H01L21/331

CPC分类号： H01L29/41708 ,  H01L29/66242 ,  H01L29/66287 ,  H01L29/732 ,  H01L29/7371

摘要： A method of fabricating an heterojunction bipolar transistor (HBT) structure in a bipolar complementary metal-oxide-semiconductor (BiCMOS) process selectively thickens an oxide layer overlying a base region in areas that are not covered by a temporary emitter and spacers such that the temporary emitter can be removed and the base-emitter junction can be exposed without also completely removing the oxide overlying the areas of the base region that are not covered by the temporary emitter or spacers. As a result, a photomask is not required to remove the temporary emitter and to expose the base-emitter junction.

摘要翻译： 在双极互补金属氧化物半导体（BiCMOS）工艺中制造异质结双极晶体管（HBT）结构的方法在未被临时发射极和间隔物覆盖的区域中的基极区域上选择性地增厚氧化物层，使得临时 可以去除发射极，并且可以暴露基极 - 发射极结，而不会完全去除覆盖在未被临时发射极或间隔物覆盖的基极区域的区域上的氧化物。 结果，不需要光掩模去除临时发射体并露出基极 - 发射极结。

公开(公告)号：US20080308940A1

公开(公告)日：2008-12-18

申请号：US12198196

申请日：2008-08-26

申请人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

发明人： Natalie Barbara Feilchenfeld ,  Zhong-Xiang He ,  Qizhi Liu ,  BethAnn Rainey ,  Ping-Chuan Wang ,  Kimball M. Watson

IPC分类号： H01L23/522

CPC分类号： H01L21/76838 ,  H01L21/8249 ,  H01L23/53228 ,  H01L23/53257 ,  H01L23/53295 ,  H01L27/0623 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor structure. The semiconductor structure includes (a) a substrate; (b) a first semiconductor device on the substrate; (c) N ILD (Inter-Level Dielectric) layers on the first semiconductor device, wherein N is an integer greater than one; and (d) an electrically conductive line electrically coupled to the first semiconductor device. The electrically conductive line is adapted to carry a lateral electric current in a lateral direction parallel to an interfacing surface between two consecutive ILD layers of the N ILD layers. The electrically conductive line is present in at least two ILD layers of the N ILD layers. The electrically conductive line does not comprise an electrically conductive via that is adapted to carry a vertical electric current in a vertical direction perpendicular to the interfacing surface.

摘要翻译： 半导体结构。 半导体结构包括（a）基板; （b）基板上的第一半导体器件; （c）第一半导体器件上的N ILD（层间电介质）层，其中N是大于1的整数; 和（d）电耦合到第一半导体器件的导电线。 导电线适于在平行于N个ILD层的两个连续ILD层之间的界面表面的横向方向上承载横向电流。 导电线路存在于N ILD层的至少两个ILD层中。 导电线不包括适于在垂直于接口表面的垂直方向承载垂直电流的导电通孔。

公开(公告)号：US07265018B2

公开(公告)日：2007-09-04

申请号：US10711486

申请日：2004-09-21

申请人： James S. Dunn ,  Alvin J. Joseph ,  Qizhi Liu

发明人： James S. Dunn ,  Alvin J. Joseph ,  Qizhi Liu

IPC分类号： H01L21/8222

CPC分类号： H01L29/66242 ,  H01L29/7378

摘要： The present invention provides a method of forming a self-aligned heterobipolar transistor (HBT) device in a BiCMOS technology. The method includes forming a raised extrinsic base structure by using an epitaxial growth process in which the growth rate between single crystal silicon and polycrystalline silicon is different and by using a low temperature oxidation process such as a high-pressure oxidation (HIPOX) process to form a self-aligned emitter/extrinsic base HBT structure.

摘要翻译： 本发明提供了一种在BiCMOS技术中形成自对准异双极晶体管（HBT）器件的方法。 该方法包括通过使用其中单晶硅和多晶硅的生长速率不同的外延生长工艺和通过使用诸如高压氧化（HIPOX）工艺的低温氧化工艺形成凸起的外在基体结构来形成 自对准发射极/非本征基极HBT结构。

公开(公告)号：US07217628B2

公开(公告)日：2007-05-15

申请号：US10905685

申请日：2005-01-17

申请人： David C. Sheridan ,  Peter B. Gray ,  Jeffrey B. Johnson ,  Qizhi Liu

发明人： David C. Sheridan ,  Peter B. Gray ,  Jeffrey B. Johnson ,  Qizhi Liu

IPC分类号： H01L21/8228

CPC分类号： H01L29/66242 ,  H01L21/82285 ,  H01L27/0826 ,  H01L29/0821 ,  H01L29/7378

摘要： A complementary bipolar transistor is fabricated using an available portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collector layer. The complementary pair of transistors is vertically aligned and operates in a single direction.

摘要翻译： 使用硅锗（SiGe）低温外延层的可用部分作为垂直NPN晶体管的升高的基极区域和与垂直PNP集电极层相同的SiGe LTE层的另一部分来制造互补双极晶体管。 互补的晶体管对垂直对齐并在单个方向上工作。

公开(公告)号：US07119416B1

公开(公告)日：2006-10-10

申请号：US11169444

申请日：2005-06-29

申请人： Thomas N. Adam ,  Kevin K. Chan ,  Alvin J. Joseph ,  Marwan H. Khater ,  Qizhi Liu ,  Beth Ann Rainey ,  Kathryn T. Schonenberg

发明人： Thomas N. Adam ,  Kevin K. Chan ,  Alvin J. Joseph ,  Marwan H. Khater ,  Qizhi Liu ,  Beth Ann Rainey ,  Kathryn T. Schonenberg

IPC分类号： H01L27/82 ,  H01L29/70

CPC分类号： H01L29/7378 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/66287

摘要： The invention includes methods of fabricating a bipolar transistor that adds a silicon germanium (SiGe) layer or a third insulator layer of, e.g., high pressure oxide (HIPOX), atop an emitter cap adjacent the intrinsic base prior to forming a link-up layer. This addition allows for removal of the link-up layer using wet etch chemistries to remove the excess SiGe or third insulator layer formed atop the emitter cap without using oxidation. In this case, an oxide section (formed by deposition of an oxide or segregation of the above-mentioned HIPOX layer) and nitride spacer can be used to form the emitter-base isolation. The invention results in lower thermal cycle, lower stress levels, and more control over the emitter cap layer thickness, which are drawbacks of the first embodiment. The invention also includes the resulting bipolar transistor structure.

公开(公告)号：US20060157823A1

公开(公告)日：2006-07-20

申请号：US10905685

申请日：2005-01-17

申请人： David Sheridan ,  Peter Gray ,  Jeffrey Johnson ,  Qizhi Liu

发明人： David Sheridan ,  Peter Gray ,  Jeffrey Johnson ,  Qizhi Liu

IPC分类号： H01L27/082

CPC分类号： H01L29/66242 ,  H01L21/82285 ,  H01L27/0826 ,  H01L29/0821 ,  H01L29/7378

摘要： A complementary bipolar transistor is fabricated using an available a portion of a silicon germanium (SiGe) low temperature epitaxial layer as the raised base region for a vertical NPN transistor, and another portion of the same SiGe LTE layer as a vertical PNP collector layer. The complementary pair of transistors is vertically aligned and operates in a single direction.

摘要翻译： 使用可用的硅锗（SiGe）低温外延层的一部分作为垂直NPN晶体管的升高的基极区域和与垂直PNP集电极层相同的SiGe LTE层的另一部分来制造互补双极晶体管。 互补的晶体管对垂直对齐并在单个方向上工作。

公开(公告)号：US06965133B2

公开(公告)日：2005-11-15

申请号：US10708598

申请日：2004-03-13

申请人： Peter J. Geiss ,  Marwan H. Khater ,  Qizhi Liu ,  Randy W. Mann ,  Robert J. Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas D. Stricker

发明人： Peter J. Geiss ,  Marwan H. Khater ,  Qizhi Liu ,  Randy W. Mann ,  Robert J. Purtell ,  BethAnn Rainey ,  Jae-Sung Rieh ,  Andreas D. Stricker

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/417 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/66242 ,  H01L21/28518 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0804 ,  H01L29/456 ,  H01L29/7371

摘要： Methods for fabricating a heterojunction bipolar transistor having a raised extrinsic base is provided in which the base resistance is reduced by forming a silicide atop the raised extrinsic base that extends to the emitter region in a self-aligned manner. The silicide formation is incorporated into a BiCMOS process flow after the raised extrinsic base has been formed. The present invention also provides a heterojunction bipolar transistor having a raised extrinsic base and a silicide located atop the raised extrinsic base. The silicide atop the raised extrinsic base extends to the emitter in a self-aligned manner. The emitter is separated from the silicide by a spacer.

摘要翻译： 提供了制造具有凸起非本征基极的异质结双极晶体管的方法，其中通过在以自对准方式延伸到发射极区域的凸起的外部基极之上形成硅化物来降低基极电阻。 在形成凸起的外基之后，将硅化物形成结合到BiCMOS工艺流程中。 本发明还提供了一种异质结双极晶体管，其具有凸起的外部基极和位于凸起外部基极顶部的硅化物。 凸起的外基极上面的硅化物以自对准的方式延伸到发射极。 发射极通过间隔物与硅化物分离。

公开(公告)号：US06869852B1

公开(公告)日：2005-03-22

申请号：US10707756

申请日：2004-01-09

申请人： Alvin J. Joseph ,  Qizhi Liu ,  BethAnn Rainey ,  Kathryn T. Schonenberg

发明人： Alvin J. Joseph ,  Qizhi Liu ,  BethAnn Rainey ,  Kathryn T. Schonenberg

IPC分类号： H01L21/331 ,  H01L29/10 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/66287 ,  H01L29/1004 ,  H01L29/66242

摘要： A method of fabricating a bipolar transistor structure that provides unit current gain frequency (fT) and maximum oscillation frequency (fMAX) improvements of a raised extrinsic base using non-self-aligned techniques to establish a self-aligned structure. Accordingly, the invention eliminates the complexity and cost of current self-aligned raised extrinsic base processes. The invention forms a raised extrinsic base and an emitter opening over a landing pad, i.e., etch stop layer, then replaces the landing pad with a conductor that is converted, in part, to an insulator. An emitter is then formed in the emitter opening once the insulator is removed from the emitter opening. An unconverted portion of the conductor provides a conductive base link and a remaining portion of the insulator under a spacer isolates the extrinsic base from the emitter while maintaining self-alignment of the emitter to the extrinsic base. The invention also includes the resulting bipolar transistor structure.

摘要翻译： 一种制造双极晶体管结构的方法，其使用非自对准技术建立自对准结构来提供升高的外部基极的单位电流增益频率（fT）和最大振荡频率（fMAX）改善。 因此，本发明消除了当前自对准引起的外在基本过程的复杂性和成本。 本发明形成凸起的非本征基极和在着陆焊盘（即，蚀刻停止层）上开口的发射体，然后用部分转换为绝缘体的导体代替着陆焊盘。 一旦绝缘体从发射极开口移除，就在发射极开口中形成发射极。 导体的未转换部分提供导电基极连接，并且在间隔物下方的绝缘体的剩余部分将外部基极与发射极隔离，同时保持发射极到外部基极的自对准。 本发明还包括所得到的双极晶体管结构。

公开(公告)号：US09059138B2

公开(公告)日：2015-06-16

申请号：US13358180

申请日：2012-01-25

申请人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

发明人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

IPC分类号： H01L29/737 ,  G06F17/50 ,  H01L21/331 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10

CPC分类号： H01L29/417 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371

摘要： A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.

摘要翻译： 提供异质结双极晶体管（HBT）结构，其制造方法及其设计结构。 HBT结构包括其中具有亚集电极区域的半导体衬底。 HBT结构还包括覆盖子集电极区域的一部分的集电极区域。 HBT结构还包括覆盖集电极区域的至少一部分的本征基极层。 HBT结构还包括与本征基极层相邻并电连接的外部基极层。 HBT结构还包括在外部基极层和副集电极区之间垂直延伸的隔离区。 HBT结构还包括覆盖本征基极层的一部分的发射极。 HBT结构还包括电连接到子集电极区的集电极触点。 收集器触点有利地延伸穿过外部基极层的至少一部分。