公开(公告)号：US20150033044A1

公开(公告)日：2015-01-29

申请号：US14452373

申请日：2014-08-05

Applicant: Rambus Inc.

Inventor： Ely Tsern ,  Thomas Vogelsang ,  Craig Hampel ,  Scott C. Best

IPC: G06F3/06 ,  G06F1/26 ,  G11C5/14

CPC classification number: G06F3/0625 ,  G06F1/266 ,  G06F3/0634 ,  G06F3/0673 ,  G11C5/147 ,  G11C11/4074 ,  G11C2207/2227

Abstract: A memory system supports high-performance and low-power modes. The memory system includes a memory core and a core interface. The memory core employs core supply voltages that remain the same in both modes. Supply voltages and signaling rates for the core interface may be scaled down to save power. Level shifters between the memory core and core interface level shift signals as needed to accommodate the signaling voltages used by the core interface in the different modes.

Abstract translation: 内存系统支持高性能和低功耗模式。 存储器系统包括存储器核和核心接口。 存储器内核采用在两种模式下保持相同的核心电源电压。 核心接口的电源电压和信号速率可以缩小以节省功耗。 存储器核心和核心接口电平之间的电平移位器根据需要移位信号以适应不同模式下核心接口所使用的信令电压。

公开(公告)号：US20140351629A1

公开(公告)日：2014-11-27

申请号：US14285481

申请日：2014-05-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern

IPC: G06F11/20

CPC classification number: G06F11/1044 ,  G06F11/1048 ,  G06F11/1068 ,  G06F11/1666 ,  G06F11/20 ,  G11C7/10 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/70 ,  G11C29/765 ,  G11C2029/4402 ,  H03M13/1575

Abstract: A memory module is disclosed that includes a substrate, a memory device that outputs read data, and a buffer. The buffer has a primary interface for transferring the read data to a memory controller and a secondary interface coupled to the memory device to receive the read data. The buffer includes error logic to identify an error in the received read data and to identify a storage cell location in the memory device associated with the error. Repair logic maps a replacement storage element as a substitute storage element for the storage cell location associated with the error.

Abstract translation: 公开了一种存储器模块，其包括衬底，输出读取数据的存储器件和缓冲器。 缓冲器具有用于将读取的数据传送到存储器控制器的主界面和耦合到存储器设备的辅助接口以接收读取的数据。 缓冲器包括用于识别所接收的读取数据中的错误并识别与该错误相关联的存储器件中的存储单元位置的错误逻辑。 修复逻辑将替换存储元素映射为与错误相关联的存储单元位置的替代存储元素。

公开(公告)号：US20140293710A1

公开(公告)日：2014-10-02

申请号：US14351955

申请日：2012-10-26

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely Tsern ,  Brian Leibowitz ,  Jared Zerbe

IPC: H03K5/13 ,  G11C7/22

CPC classification number: H03K5/13 ,  G06F13/00 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/04 ,  G11C7/1066 ,  G11C7/1093 ,  G11C7/22 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028

Abstract: An integrated circuit includes a delay circuit and first and second interface circuits. The delay circuit delays a first timing signal by an internal delay to generate an internal timing signal. The first interface circuit communicates data to an external device in response to the internal timing signal. The second interface circuit transmits an external timing signal for capturing the data in the external device. An external delay is added to the external timing signal in the external device to generate a delayed external timing signal. The delay circuit sets the internal delay based on a comparison between the delayed external timing signal and a calibration signal transmitted by the first interface circuit.

Abstract translation: 集成电路包括延迟电路和第一和第二接口电路。 延迟电路将第一定时信号延迟内部延迟以产生内部定时信号。 第一接口电路响应于内部定时信号将数据传送到外部设备。 第二接口电路发送用于捕获外部设备中的数据的外部定时信号。 外部延迟被添加到外部设备中的外部定时信号以产生延迟的外部定时信号。 延迟电路基于延迟的外部定时信号和由第一接口电路发送的校准信号之间的比较来设置内部延迟。