公开(公告)号：US07839681B2

公开(公告)日：2010-11-23

申请号：US12334059

申请日：2008-12-12

申请人： Zhigang Wang ,  Fethi Dhaoui ,  Michael Sadd ,  John McCollum ,  Frank Hawley

发明人： Zhigang Wang ,  Fethi Dhaoui ,  Michael Sadd ,  John McCollum ,  Frank Hawley

IPC分类号： G11C11/34

CPC分类号： G11C16/0441

摘要： A flash memory cell includes a p-channel flash transistor having a source, a drain, a floating gate, and a control gate, an n-channel flash transistor having a source, a drain coupled to the drain of the p-channel flash transistor, a floating gate, and a control gate, a switch transistor having a gate coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source, and a drain, and an n-channel assist transistor having a drain coupled to the drains of the p-channel flash transistor and the n-channel flash transistor, a source coupled to a fixed potential, and a gate.

摘要翻译： 闪存单元包括具有源极，漏极，浮置栅极和控制栅极的p沟道闪存晶体管，具有源极的n沟道闪存晶体管，耦合到p沟道闪存晶体管的漏极的漏极 ，浮动栅极和控制栅极，具有耦合到p沟道闪存晶体管和n沟道闪存晶体管的漏极的栅极的开关晶体管，源极和漏极以及n沟道辅助晶体管，其具有 漏极，其耦合到p沟道闪存晶体管和n沟道闪存晶体管的漏极，耦合到固定电位的源极和栅极。

公开(公告)号：US07721172B2

公开(公告)日：2010-05-18

申请号：US12216640

申请日：2008-07-09

申请人： Laung-Terng (L.-T.) Wang ,  Boryau (Jack) Sheu ,  Zhigang Jiang ,  Zhigang Wang ,  Shianling Wu

发明人： Laung-Terng (L.-T.) Wang ,  Boryau (Jack) Sheu ,  Zhigang Jiang ,  Zhigang Wang ,  Shianling Wu

IPC分类号： G01R31/28 ,  G06F17/50

CPC分类号： G01R31/318547 ,  G01R31/318533 ,  G01R31/318591 ,  G01R31/31926

摘要： A broadcaster, system, and method for reducing test data volume and test application time in an ATE (automatic test equipment) in a scan-based integrated circuit. The scan-based integrated circuit contains multiple scan chains, each scan chain comprising multiple scan cells coupled in series. The broadcaster is a combinational logic network coupled to an optional virtual scan controller and an optional scan connector. The virtual scan controller controls the operation of the broadcaster. The system transmits virtual scan patterns stored in the ATE and generates broadcast scan patterns through the broadcaster for testing manufacturing faults in the scan-based integrated circuit. The number of scan chains that can be supported by the ATE is significantly increased. Methods are further proposed to reorder scan cells in selected scan chains, to generate the broadcast scan patterns and virtual scan patterns, and to synthesize the broadcaster and a compactor in the scan-based integrated circuit.The scan architecture used can also be random access scan based, where the integrated circuit comprises an array of random access scan (RAS) cells that are randomly and uniquely addressable. In random access scan, test patterns can be applied by selectively updating RAS cells and test responses can be observed through a direct read-out process. Eliminating the shifting process inherent in serial scan, random access scan produces much lower test power dissipation than serial scan.

摘要翻译： 用于在基于扫描的集成电路中的ATE（自动测试设备）中降低测试数据量和测试应用时间的广播，系统和方法。 基于扫描的集成电路包含多个扫描链，每个扫描链包括串联耦合的多个扫描单元。 广播公司是组合逻辑网络，耦合到可选的虚拟扫描控制器和可选的扫描连接器。 虚拟扫描控制器控制广播机构的操作。 系统发送存储在ATE中的虚拟扫描模式，并通过广播机构生成广播扫描模式，以测试基于扫描的集成电路中的制造故障。 ATE可以支持的扫描链数显着增加。 进一步提出了方法来重新排列所选择的扫描链中的扫描单元，以产生广播扫描图案和虚拟扫描图案，并且在基于扫描的集成电路中合成广播器和压缩器。 所使用的扫描结构也可以是基于随机存取扫描的集成电路，其中集成电路包括随机访问扫描（RAS）阵列，其随机且唯一可寻址。 在随机存取扫描中，可以通过选择性地更新RAS细胞来应用测试模式，并且可以通过直接读出过程来观察测试响应。 消除串行扫描固有的移位过程，随机访问扫描产生比串行扫描低得多的测试功耗。

公开(公告)号：US20100038697A1

公开(公告)日：2010-02-18

申请号：US12370828

申请日：2009-02-13

申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  William C. Plants ,  Zhigang Wang

IPC分类号： H01L27/115 ,  H01L29/788

CPC分类号： H01L27/11524 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/7881

摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

摘要翻译： 在半导体本体中形成双晶体管非易失性存储单元。 记忆晶体管阱设置在半导体本体内。 开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。 包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。 在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。 浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。 控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

公开(公告)号：US20090159954A1

公开(公告)日：2009-06-25

申请号：US12359481

申请日：2009-01-26

申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

IPC分类号： H01L29/788

CPC分类号： H01L27/0203 ,  H01L21/823493 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

公开(公告)号：US20090052015A1

公开(公告)日：2009-02-26

申请号：US12195864

申请日：2008-08-21

申请人： Zhigang Wang ,  Aihua Yu

发明人： Zhigang Wang ,  Aihua Yu

IPC分类号： H01S3/00

CPC分类号： H01S3/06754 ,  H01S3/0014 ,  H01S3/1616 ,  H01S2301/04

摘要： A method for acquiring spectrum shape of a gain flattening filter of a doped optical fiber amplifier comprises the steps of: measuring spectrum shapes at two gain point (H, L) of the doped optical fiber with invariable fiber length respectively; and acquiring various gain spectrums of the doped optical fiber with various fiber length and various population inversion level according to an expression: ErGain(λ,x,L′)=[ErLGain(λ)+[ErHGain(λ)−ErLGain(λ)]*x]*L′, Wherein Gain(λ) refers to the spectral function of gain, x is Δ′inv/Δinv which refers to change of population inversion level, and L′ is set as proportion of doped fiber length. Gain spectrums of the doped optical fiber with various fiber length can be acquired by measuring spectrum shapes at two gain point (H, L) of the doped optical fiber in invariable fiber length and applying change rule of gain spectrum of the doped optical fiber in different population inversion level, which improves the flexibility for design of amplifier.

摘要翻译： 一种用于获取掺杂光纤放大器的增益平坦滤波器的光谱形状的方法，包括以下步骤：分别测量具有不变光纤长度的掺杂光纤的两个增益点（H，L）处的光谱形状; 并且根据以下表达式获取具有各种光纤长度和各种总体反转电平的掺杂光纤的各种增益光谱：<？in-line-formula description =“In-line Formulas”end =“lead”？> ErGain（λ， x，L'）= [ErLGain（lambda）+ [ErHGain（lambda）-ErLGain（lambda）] * x] * L'，<？in-line-formula description =“In-line Formulas”end =“tail” ？>其中增益（lambda）是指增益的光谱函数，x是Delta'inv / Deltainv，其指的是群体反转级别的变化，L'被设置为掺杂光纤长度的比例。 通过以不变的光纤长度测量掺杂光纤的两个增益点（H，L）处的光谱形状，并将掺杂光纤的增益光谱的变化规则应用于不同的光纤中，可以获得具有各种光纤长度的掺杂光纤的增益谱 人口反演水平提高了放大器设计的灵活性。

公开(公告)号：US07418683B1

公开(公告)日：2008-08-26

申请号：US11233809

申请日：2005-09-21

申请人： Jean-Daniel Sonnard ,  Zhigang Wang ,  Hemanth Sampath

发明人： Jean-Daniel Sonnard ,  Zhigang Wang ,  Hemanth Sampath

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/74

摘要： A computer aided design tool and method for designing IC layouts by recommending subcircuit layout constraints based upon an automated identification from a circuit schematic of subcircuit types requiring special IC layout constraints. Subcircuit types are identified on the basis of netlist examination, as well as cues from the layout of the circuit schematic.

摘要翻译： 一种用于设计IC布局的计算机辅助设计工具和方法，其通过基于需要特殊IC布局约束的子电路类型的电路原理图的自动识别来推荐子电路布局约束。 基于网表检查的子电路类型，以及电路原理图布局的线索。

公开(公告)号：US20070215935A1

公开(公告)日：2007-09-20

申请号：US11750650

申请日：2007-05-18

申请人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

发明人： Fethi Dhaoui ,  John McCollum ,  Vidyadhara Bellippady ,  Zhigang Wang

IPC分类号： H01L29/788

CPC分类号： H01L27/0203 ,  H01L21/823493 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.

摘要翻译： 在半导体本体中形成双晶体管非易失性存储单元。 记忆晶体管阱设置在半导体本体内。 开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。 包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。 在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。 浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。 控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。

公开(公告)号：US20060023511A1

公开(公告)日：2006-02-02

申请号：US10909693

申请日：2004-08-02

申请人： Zhigang Wang ,  Nian Yang ,  Zhizheng Liu

发明人： Zhigang Wang ,  Nian Yang ,  Zhizheng Liu

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/12

摘要： Disclosed are a flash memory unit and a method of programming a flash memory device. The method of programming can include applying respective programming voltages to a control gate and a drain of the memory device. A source bias potential can be applied to a source of the memory device. The application of the source bias potential can be controlled with the selective application of one of the programming voltages to a source bias switching device.

摘要翻译： 公开了一种闪速存储器单元和一种对闪速存储器件进行编程的方法。 编程的方法可以包括将相应的编程电压施加到存储器件的控制栅极和漏极。 源极偏置电位可以应用于存储器件的源极。 可以通过选择性地将一个编程电压施加到源极偏置开关器件来控制源极偏置电位的应用。

公开(公告)号：US06987696B1

公开(公告)日：2006-01-17

申请号：US10885268

申请日：2004-07-06

申请人： Zhigang Wang ,  Nian Yang ,  Shenqing Fang

发明人： Zhigang Wang ,  Nian Yang ,  Shenqing Fang

IPC分类号： G11C16/00

CPC分类号： G11C16/16 ,  G11C16/0491 ,  H01L27/115

摘要： Techniques for erasing memory devices of a flash memory array having a plurality of operative wordlines and at least one dummy wordline adjacent an end one of the operative wordlines are disclosed. Erasing the memory devices can include applying a gate voltage to the wordlines and applying a bias voltage to the dummy wordlines. In one arrangement, an electrical connection is established between the dummy wordline and the end one of the operative wordlines.

摘要翻译： 公开了一种用于擦除具有多个操作字线的闪速存储器阵列的存储器件以及与操作字线的末端相邻的至少一个伪字线的技术。 擦除存储器件可以包括将栅极电压施加到字线并将偏置电压施加到伪字线。 在一种布置中，在伪字线和操作字线的末端之间建立电连接。

公开(公告)号：US06963506B1

公开(公告)日：2005-11-08

申请号：US10679179

申请日：2003-10-03

申请人： Zhigang Wang ,  Nian Yang ,  Yue-Song He

发明人： Zhigang Wang ,  Nian Yang ,  Yue-Song He

IPC分类号： G11C16/06 ,  G11C16/26 ,  G11C16/30

CPC分类号： G11C16/30 ,  G11C16/26

摘要： An exemplary sensing circuit for sensing the current drawn by a target memory cell comprises a first transistor connected across a first node and a second node, a load connected across the second node and a third node, and a voltage boosting circuit coupled to a supply voltage, wherein the voltage boosting circuit supplies a voltage at the third node which is greater than the supply voltage.

摘要翻译： 用于感测由目标存储器单元汲取的电流的示例性感测电路包括跨越第一节点和第二节点连接的第一晶体管，跨过第二节点连接的负载和第三节点，以及耦合到电源电压的升压电路 ，其中所述升压电路在所述第三节点处提供大于所述电源电压的电压。