公开(公告)号：US11411078B2

公开(公告)日：2022-08-09

申请号：US16701427

申请日：2019-12-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyojoon Ryu ,  Kiyoon Kang ,  Seogoo Kang ,  Shinhwan Kang ,  Jesuk Moon ,  Byunggon Park ,  Jaeryong Sim ,  Jinsoo Lim ,  Jisung Cheon ,  Jeehoon Han

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L29/06 ,  H01L23/31 ,  G11C5/06 ,  H01L27/1157 ,  H01L27/11573

Abstract: A semiconductor device including a substrate having a cell, peripheral, and boundary area; a stack structure on the cell area and including insulating and interconnection layers that are alternately stacked; a molding layer on the peripheral area boundary areas; a selection line isolation pattern extending into the stack structure; a cell channel structure passing through the stack structure; and first dummy patterns extending into the molding layer on the peripheral area, wherein upper surfaces of the first dummy patterns, an upper surface of the selection line isolation pattern, and an upper surface of the cell channel structure are coplanar, and at least one of the first dummy patterns extends in parallel with the selection line isolation pattern or cell channel structure from upper surfaces of the first dummy patterns, the upper surface of the selection line isolation pattern, and the upper surface of the cell channel structure toward the substrate.

公开(公告)号：US11121151B2

公开(公告)日：2021-09-14

申请号：US16562919

申请日：2019-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan Kang ,  Younghwan Son ,  Haemin Lee ,  Kohji Kanamori ,  Jeehoon Han

IPC: H01L27/00 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/1157

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

公开(公告)号：US11049847B2

公开(公告)日：2021-06-29

申请号：US16734505

申请日：2020-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji Kanamori ,  Yongseok Kim ,  Kyunghwan Lee ,  Junhee Lim ,  Jeehoon Han

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor device includes a first semiconductor structure comprising a substrate and a circuit element, and a second semiconductor structure connected to the first semiconductor structure. The second semiconductor structure includes a base layer, a first memory cell structure, a second memory cell structure, and common bit lines between the first memory cell structure and the second memory cell structure. The first memory cell structure includes first gate electrodes, first channel structures, and first string select channel structures. The second memory cell structure includes second gate electrodes, second channel structures, second string select channel structures, and connection regions between the second channel structures and the second string select channel structures. The first memory cell structure further includes first channel pads between the common bit lines and the first string select channel structures, and the second memory cell structure further includes second channel pads extending along the common bit lines.

公开(公告)号：US20200251417A1

公开(公告)日：2020-08-06

申请号：US16853850

申请日：2020-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-Hun Lee ,  Seokjung Yun ,  Chang-Sup Lee ,  Seong Soon Cho ,  Jeehoon Han

IPC: H01L23/528 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L21/768 ,  H01L27/11575 ,  H01L27/11565 ,  H01L27/11556 ,  H01L27/11551 ,  H01L27/11578

Abstract: A three-dimensional (3D) semiconductor device includes a stack structure including first and second stacks stacked on a substrate. Each of the first and second stacks includes a first electrode and a second electrode on the first electrode. A sidewall of the second electrode of the first stack is horizontally spaced apart from a sidewall of the second electrode of the second stack by a first distance. A sidewall of the first electrode is horizontally spaced apart from the sidewall of the second electrode by a second distance in each of the first and second stacks. The second distance is smaller than a half of the first distance.

公开(公告)号：US09508551B2

公开(公告)日：2016-11-29

申请号：US14665141

申请日：2015-03-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hojun Seong ,  Jae-Hwang Sim ,  Jeehoon Han

IPC: H01L21/00 ,  H01L23/00 ,  H01L27/00 ,  H01L29/00 ,  H01L21/033 ,  H01L21/768 ,  H01L27/115 ,  H01L23/528 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/76892 ,  H01L21/76895 ,  H01L23/528 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11573 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of fabricating a semiconductor device includes stacking an etch target layer, a first mask layer, and a second mask layer on a first surface of a substrate. A plurality of first spacer lines are formed parallel to each other and a first spacer pad line on the second mask layer is formed. A third mask pad in contact with at least the first spacer pad line on the second mask layer is formed. The second mask layer and the first mask layer are etched to form one or more first mask lines, a first mask preliminary pad, and second mask patterns. Second spacer lines are respectively formed covering sidewalls of the first mask preliminary pad and the first mask lines. First mask pads are formed. The etch target layer is etched to form conductive lines and conductive pads connected to the conductive lines.

Abstract translation: 制造半导体器件的方法包括在衬底的第一表面上堆叠蚀刻目标层，第一掩模层和第二掩模层。 多个第一间隔线彼此平行地形成，并且形成第二掩模层上的第一间隔垫线。 形成与第二掩模层上的至少第一间隔垫线接触的第三掩模焊盘。 蚀刻第二掩模层和第一掩模层以形成一个或多个第一掩模线，第一掩模预焊垫和第二掩模图案。 分别形成覆盖第一掩模预备焊盘和第一掩模线的侧壁的第二间隔线。 形成第一掩模垫。 蚀刻目标层被蚀刻以形成连接到导线的导电线和导电焊盘。