公开(公告)号：US20230154541A1

公开(公告)日：2023-05-18

申请号：US17530196

申请日：2021-11-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jiahui Yuan ,  Deepanshu Dutta

IPC: G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C16/30 ,  G11C7/10

CPC classification number: G11C16/14 ,  G11C16/102 ,  G11C16/26 ,  G11C16/08 ,  G11C16/0433 ,  G11C16/30 ,  G11C7/1048

Abstract: Programming a plurality of non-volatile memory cells includes performing a soft erase process during the programming. The soft erase process includes pre-charging channels of the memory cells and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging.

公开(公告)号：US20230056891A1

公开(公告)日：2023-02-23

申请号：US17406224

申请日：2021-08-19

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Deepanshu Dutta ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/04 ,  G11C16/30

Abstract: Apparatuses and techniques are described for controlling a bit line pre-charge voltage in a program operation based on a number of bits per cell, with a goal to reduce peak current consumption. In one aspect, the ramp up of a bit line voltage to an inhibit level is optimized according to the number of bits per cell. The ramp up can involve increasing the bit line voltage from an initial level to a target voltage at a regulated rate, then increasing the bit line voltage from the target voltage to a final voltage at an unregulated rate. In one approach, the regulated ramp rate is less for single-level cell programming compared to multi-level cell programming. The target voltage can also be optimized based on the number of bis per cell.

公开(公告)号：US11532370B1

公开(公告)日：2022-12-20

申请号：US17329304

申请日：2021-05-25

Applicant: SanDisk Technologies LLC

Inventor： Xiang Yang ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G11C11/34 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C11/56 ,  H01L27/11565 ,  G11C16/04 ,  H01L25/065 ,  H01L27/11582

Abstract: To improve programming performance for a non-volatile memory , the verification of multiple programming levels can be performed based on a single discharge of a sensing capacitor through a selected memory cell by using different voltage levels on a second plate of the sensing capacitor: after discharging a first plate of the sensing capacitor through the selected memory cell, a result amount of charge is trapped on the first plate, which is then used to set first and second control gate voltages on a sensing transistor whose control gate is connected to the first place of the sensing capacitor based on respectively setting the second plate of the sensing capacitor to first and second voltage levels. To further improve programming performance, when the non-volatile memory stores in a multistate format, after the next to highest data state finishes programming, the next programming pulse can use a larger step size.

公开(公告)号：US11481154B2

公开(公告)日：2022-10-25

申请号：US17149867

申请日：2021-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Deepanshu Dutta ,  James Kai ,  Johann Alsmeier ,  Jian Chen

IPC: G06F3/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  H01L27/11582 ,  G11C16/04 ,  H01L27/11565

Abstract: An integrated memory assembly comprises a memory die and a control die bonded to the memory die. The memory die comprises a three dimensional non-volatile memory structure and a first plurality of sense amplifiers. The first plurality of sense amplifiers are connected to the memory structure and are positioned on a substrate of the memory die between the memory structure and the substrate such that the memory structure is directly above the first plurality of sense amplifiers. The control die comprises a second plurality of sense amplifiers that are connected to the memory structure. The first plurality of sense amplifiers and the second plurality of sense amplifiers are configured to be used to concurrently perform memory operations.

公开(公告)号：US11475961B1

公开(公告)日：2022-10-18

申请号：US17307396

申请日：2021-05-04

Applicant: SanDisk Technologies LLC

Inventor： Sujjatul Islam ,  Ravi J. Kumar ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/14 ,  G11C16/10 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26

Abstract: An apparatus includes one or more control circuits configured to connect to a plurality of non-volatile memory cells through a plurality of word lines. The one or more control circuits are configured to, for each target word line of a plurality of target word lines to be read, select either a first neighboring word line or a second neighboring word line as a selected neighboring word line according to whether non-volatile memory cells of the first neighboring word line are in an erased condition. The one or more control circuits are further configured to determine a read voltage to read non-volatile memory cells of a corresponding target word line according to an amount of charge in non-volatile memory cells of the selected neighboring word line.

公开(公告)号：US20220310179A1

公开(公告)日：2022-09-29

申请号：US17212871

申请日：2021-03-25

Applicant: SanDisk Technologies LLC

Inventor： Fanqi Wu ,  Deepanshu Dutta ,  Huai-Yuan Tseng

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11582

Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase pulse to a first grouping of non-volatile storage elements; after applying the first erase pulse, determining an upper tail of a threshold voltage distribution of the first grouping of non-volatile storage elements; determining a difference between the upper tail of the first grouping of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second grouping of non-volatile storage elements; and disabling, in a second erase loop of the plurality of erase loops, the erase operation on the first grouping of non-volatile storage elements if the difference is greater than or equal to the threshold amount.

公开(公告)号：US11437110B1

公开(公告)日：2022-09-06

申请号：US17212871

申请日：2021-03-25

Applicant: SanDisk Technologies LLC

Inventor： Fanqi Wu ,  Deepanshu Dutta ,  Huai-Yuan Tseng

IPC: G11C16/00 ,  G11C16/34 ,  G11C16/16 ,  G11C16/04 ,  H01L27/11524 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11529

Abstract: A method of performing an erase operation on non-volatile storage is disclosed. The method comprises: applying, in a first erase loop of a plurality of erase loops of the erase operation, a first erase pulse to a first grouping of non-volatile storage elements; after applying the first erase pulse, determining an upper tail of a threshold voltage distribution of the first grouping of non-volatile storage elements; determining a difference between the upper tail of the first grouping of non-volatile storage elements and an upper tail of a threshold voltage distribution of a second grouping of non-volatile storage elements; and disabling, in a second erase loop of the plurality of erase loops, the erase operation on the first grouping of non-volatile storage elements if the difference is greater than or equal to the threshold amount.

公开(公告)号：US20220165342A1

公开(公告)日：2022-05-26

申请号：US17102657

申请日：2020-11-24

Applicant: SanDisk Technologies LLC

Inventor： Xue Bai Pitner ,  Deepanshu Dutta ,  Ravi Kumar

IPC: G11C16/34 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: A memory apparatus and method of operation is provided. The apparatus includes a block of memory cells each connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage. A control circuit couples to the word lines and the strings determines a program lower tail voltage of a distribution of the threshold voltage following a first program pulse. The control circuit calculates a second program voltage of a second program pulse based on the program lower tail voltage and applies the second program pulse to each of selected ones of the plurality of word lines associated with the memory cells to program the memory cells such that the distribution of the threshold voltage of the memory cells have a desired program lower tail voltage without further program pulses.

公开(公告)号：US11322213B2

公开(公告)日：2022-05-03

申请号：US16899965

申请日：2020-06-12

Applicant: SanDisk Technologies LLC

Inventor： Muhammad Masuduzzaman ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C16/14 ,  G11C16/34 ,  G11C16/04

Abstract: A method comprises determining a verify voltage for a next iteration of a verify operation to be performed on memory cells a first set of memory cells of a selected word line, and determining data states for a second set of memory cells of at least one neighboring word line. The method further comprises determining, based on the data states, a verify voltage configuration that includes bit line voltage biases or sense times, and performing the next iteration of the verify operation on the selected word line by using the verify voltage configuration to iteratively verify whether respective memory cells, of the second set of memory cells, have threshold voltages above the verify voltage, wherein determining the data states, determining the verify voltage configuration, and performing the next iteration are to be repeated until a program stop condition is satisfied.

公开(公告)号：US11226772B1

公开(公告)日：2022-01-18

申请号：US16912381

申请日：2020-06-25

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Mark Murin ,  Hua-Ling Cynthia Hsu ,  Tomer Eliash ,  Huai-Yuan Tseng ,  Deepanshu Dutta

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/32 ,  H01L25/065 ,  G11C16/04

Abstract: Power and/or current regulation in non-volatile memory systems is disclosed. Peak power/current usage may be reduced by staggering concurrent program operations in the different semiconductor dies. Each set of one or more semiconductor dies has an earliest permitted start time for its program operation, as well as a number of permitted backup start times. The permitted start times are unique for each set of one or more semiconductor dies. There may be a uniform gap or delay between each permitted start time. If a semiconductor die is busy with another memory operation at or after its earliest permitted start time, then the program operation is initiated or resumed at one of the permitted backup times. By having permitted backup times, the memory system need not poll each semiconductor die to determine whether the semiconductor die is ready/busy in order to determine when a die should start a program operation.