公开(公告)号：US08809891B2

公开(公告)日：2014-08-19

申请号：US14197442

申请日：2014-03-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hisao Ikeda ,  Hiroki Ohara ,  Makoto Hosoba ,  Junichiro Sakata ,  Shunichi Ito

IPC: H01L33/00

CPC classification number: H01L51/5253 ,  G09G3/3291 ,  G09G2300/0842 ,  G09G2310/0251 ,  G09G2320/043 ,  H01L27/3211 ,  H01L27/322 ,  H01L27/3246 ,  H01L27/3272 ,  H01L51/5012 ,  H01L51/5203 ,  H01L51/5206 ,  H01L51/5234 ,  H01L51/5237 ,  H01L51/5246 ,  H01L51/525 ,  H01L51/5262 ,  H01L51/5275 ,  H01L51/5284 ,  H01L2251/301 ,  H01L2251/5315 ,  H01L2251/5323 ,  H01L2251/5338 ,  H01L2251/5361

Abstract: There has been a problem that difference in refractive index between an opposite substrate or a moisture barrier layer provided thereover, and air is maintained large, and light extraction efficiency is low. Further, there has been a problem that peeling or cracking due to the moisture barrier layer is easily generated, which leads to deteriorate the reliability and lifetime of a light-emitting element. A light-emitting element comprises a pixel electrode, an electroluminescent layer, a transparent electrode, a passivation film, a stress relieving layer, and a low refractive index layer, all of which are stacked sequentially. The stress relieving layer serves to prevent peeling of the passivation film. The low refractive index layer serves to reduce reflectivity of light generated in the electroluminescent layer in emitting to air. Therefore, a light-emitting element with high reliability and long lifetime and a display device using the light-emitting element can be provided.

Abstract translation: 存在在其上设置的相对基板或防潮层之间的折射率差异，空气保持较大，光提取效率低的问题。 此外，存在容易产生由于防潮层而产生剥离或破裂的问题，导致发光元件的可靠性和寿命恶化。 发光元件包括依次堆叠的像素电极，电致发光层，透明电极，钝化膜，应力消除层和低折射率层。 应力消除层用于防止钝化膜的剥离。 低折射率层用于降低发射到空气中的电致发光层中产生的光的反射率。 因此，可以提供具有高可靠性和长寿命的发光元件和使用该发光元件的显示装置。

公开(公告)号：US08809856B2

公开(公告)日：2014-08-19

申请号：US13784908

申请日：2013-03-05

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Miyuki Hosoba ,  Junichiro Sakata ,  Hideaki Kuwabara

IPC: H01L29/786 ,  H01L27/12

CPC classification number: H01L29/78606 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/1345 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F1/167 ,  G02F2001/13606 ,  G02F2201/123 ,  G09G3/344 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/3262 ,  H01L29/45 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

Abstract translation: 目的在于提供一种半导体器件，其具有可以有效地减少布线之间的寄生电容的结构。 在使用氧化物半导体层的底栅薄膜晶体管中，用作沟道保护层的氧化物绝缘层形成在与栅电极层重叠的氧化物半导体层的一部分上方并与其形成接触，同时氧化物 形成覆盖层叠氧化物半导体层的周边部（包括侧面）的绝缘层。 此外，以与沟道保护层不重叠的方式形成源极电极层和漏极电极层。 因此，提供了源极电极层和漏电极层上的绝缘层与氧化物半导体层接触的结构。

公开(公告)号：US08772093B2

公开(公告)日：2014-07-08

申请号：US13717806

申请日：2012-12-18

Applicant: Semiconductor Energy Laboratory Co. Ltd.

Inventor： Shunpei Yamazaki ,  Miyuki Hosoba ,  Junichiro Sakata ,  Hideaki Kuwabara

IPC: H01L21/84 ,  H01L21/00

CPC classification number: H01L29/78606 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/1345 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F1/167 ,  G02F2001/13606 ,  G02F2201/123 ,  G09G3/344 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/3262 ,  H01L29/45 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

Abstract translation: 目的在于提供一种半导体器件，其具有可以有效地减少布线之间的寄生电容的结构。 在使用氧化物半导体层的底栅薄膜晶体管中，用作沟道保护层的氧化物绝缘层形成在与栅电极层重叠的氧化物半导体层的一部分上方并与其形成接触，同时氧化物 形成覆盖层叠氧化物半导体层的周边部（包括侧面）的绝缘层。 此外，以与沟道保护层不重叠的方式形成源极电极层和漏极电极层。 因此，提供了源极电极层和漏电极层上的绝缘层与氧化物半导体层接触的结构。

公开(公告)号：US08716061B2

公开(公告)日：2014-05-06

申请号：US13718051

申请日：2012-12-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Junichiro Sakata ,  Tetsunori Maruyama ,  Yuki Imoto ,  Yuji Asano ,  Junichi Koezuka

IPC: H01L21/16

CPC classification number: H01L29/66742 ,  C04B35/58 ,  C04B2235/3284 ,  C04B2235/3286 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/7869

Abstract: In a thin film transistor which uses an oxide semiconductor, buffer layers containing indium, gallium, zinc, oxygen, and nitrogen are provided between the oxide semiconductor layer and the source and drain electrode layers.

Abstract translation: 在使用氧化物半导体的薄膜晶体管中，在氧化物半导体层和源极和漏极电极层之间设置包含铟，镓，锌，氧和氮的缓冲层。

公开(公告)号：US08698970B2

公开(公告)日：2014-04-15

申请号：US13939468

申请日：2013-07-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Junichiro Sakata ,  Masashi Tsubuku ,  Kengo Akimoto ,  Miyuki Hosoba ,  Masayuki Sakakura ,  Yoshiaki Oikawa

IPC: G02F1/136

CPC classification number: H01L21/477 ,  G02F1/133345 ,  G02F1/1368 ,  H01L21/02565 ,  H01L21/02664 ,  H01L27/1225 ,  H01L27/1248 ,  H01L27/1251 ,  H01L27/1259 ,  H01L29/66969 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a display device with excellent display characteristics, where a pixel circuit and a driver circuit provided over one substrate are formed using transistors which have different structures corresponding to characteristics of the respective circuits. The driver circuit portion includes a driver circuit transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using a metal film, and a channel layer is formed using an oxide semiconductor. The pixel portion includes a pixel transistor in which a gate electrode layer, a source electrode layer, and a drain electrode layer are formed using an oxide conductor, and a semiconductor layer is formed using an oxide semiconductor. The pixel transistor is formed using a light-transmitting material, and thus, a display device with higher aperture ratio can be manufactured.

公开(公告)号：US08597977B2

公开(公告)日：2013-12-03

申请号：US13718051

申请日：2012-12-18

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamazaki ,  Junichiro Sakata ,  Tetsunori Maruyama ,  Yuki Imoto ,  Yuji Asano ,  Junichi Koezuka

IPC: H01L21/16

Abstract: In a thin film transistor which uses an oxide semiconductor, buffer layers containing indium, gallium, zinc, oxygen, and nitrogen are provided between the oxide semiconductor layer and the source and drain electrode layers.

公开(公告)号：US08519617B2

公开(公告)日：2013-08-27

申请号：US13752589

申请日：2013-01-29

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei Yamaqzaki ,  Junichiro Sakata ,  Ryoji Nomura

IPC: H01L51/54 ,  H01J1/62

CPC classification number: H01L51/52 ,  H01L51/5048 ,  Y10S428/917

Abstract: It is an object of the present invention to provide a light emitting element with a low driving voltage. In a light emitting element, a first electrode; and a first composite layer, a second composite layer, a light emitting layer, an electron transporting layer, an electron injecting layer, and a second electrode, which are stacked over the first electrode, are included. The first composite layer and the second composite layer each include metal oxide and an organic compound. A concentration of metal oxide in the first composite layer is higher than a concentration of metal oxide in the second composite layer, whereby a light emitting element with a low driving voltage can be obtained. Further, the composite layer is not limited to a two-layer structure. A multi-layer structure can be employed. However, a concentration of metal oxide in the composite layer is gradually higher from the light emitting layer to first electrode side.

Abstract translation: 本发明的目的是提供一种具有低驱动电压的发光元件。 在发光元件中，第一电极; 并且包括层叠在第一电极上的第一复合层，第二复合层，发光层，电子传输层，电子注入层和第二电极。 第一复合层和第二复合层各自包括金属氧化物和有机化合物。 第一复合层中的金属氧化物的浓度高于第二复合层中的金属氧化物的浓度，由此可以获得具有低驱动电压的发光元件。 此外，复合层不限于两层结构。 可以采用多层结构。 然而，复合层中的金属氧化物的浓度从发光层逐渐变高到第一电极侧。

公开(公告)号：US20130130437A1

公开(公告)日：2013-05-23

申请号：US13717806

申请日：2012-12-18

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO.,LTD.

Inventor： Shunpei Yamazaki ,  Miyuki Hosoba ,  Junichiro Sakata ,  Hideaki Kuwabara

IPC: H01L29/66

CPC classification number: H01L29/78606 ,  G02F1/1339 ,  G02F1/134336 ,  G02F1/1345 ,  G02F1/136227 ,  G02F1/136286 ,  G02F1/1368 ,  G02F1/167 ,  G02F2001/13606 ,  G02F2201/123 ,  G09G3/344 ,  G09G3/3677 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/08 ,  H01L27/1218 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1255 ,  H01L27/1274 ,  H01L27/3262 ,  H01L29/45 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/786 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: An object is to provide a semiconductor device having a structure in which parasitic capacitance between wirings can be efficiently reduced. In a bottom gate thin film transistor using an oxide semiconductor layer, an oxide insulating layer used as a channel protection layer is formed above and in contact with part of the oxide semiconductor layer overlapping with a gate electrode layer, and at the same time an oxide insulating layer covering a peripheral portion (including a side surface) of the stacked oxide semiconductor layer is formed. Further, a source electrode layer and a drain electrode layer are formed in a manner such that they do not overlap with the channel protection layer. Thus, a structure in which an insulating layer over the source electrode layer and the drain electrode layer is in contact with the oxide semiconductor layer is provided.

Abstract translation: 目的在于提供一种半导体器件，其具有可以有效地减少布线之间的寄生电容的结构。 在使用氧化物半导体层的底栅薄膜晶体管中，用作沟道保护层的氧化物绝缘层形成在与栅电极层重叠的氧化物半导体层的一部分上方并与其形成接触，同时氧化物 形成覆盖层叠氧化物半导体层的周边部（包括侧面）的绝缘层。 此外，以与沟道保护层不重叠的方式形成源极电极层和漏极电极层。 因此，提供了源极电极层和漏电极层上的绝缘层与氧化物半导体层接触的结构。

公开(公告)号：US12302645B2

公开(公告)日：2025-05-13

申请号：US18214623

申请日：2023-06-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshinari Sasaki ,  Junichiro Sakata ,  Hiroki Ohara ,  Shunpei Yamazaki

IPC: H01L29/66 ,  H01L27/12 ,  H01L29/24 ,  H01L29/423 ,  H01L29/786

Abstract: It is an object to provide a highly reliable semiconductor device which includes a thin film transistor having stable electric characteristics. It is another object to manufacture a highly reliable semiconductor device at lower cost with high productivity. In a method for manufacturing a semiconductor device which includes a thin film transistor where a semiconductor layer having a channel formation region, a source region, and a drain region are formed using an oxide semiconductor layer, heat treatment (heat treatment for dehydration or dehydrogenation) is performed so as to improve the purity of the oxide semiconductor layer and reduce impurities such as moisture. Moreover, the oxide semiconductor layer subjected to the heat treatment is slowly cooled under an oxygen atmosphere.

公开(公告)号：US11257847B2

公开(公告)日：2022-02-22

申请号：US16923395

申请日：2020-07-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Junichiro Sakata ,  Toshinari Sasaki ,  Miyuki Hosoba

IPC: H01L27/12 ,  H01L21/02 ,  H01L29/786 ,  H01L29/66 ,  H01L29/24

Abstract: An object is to provide a display device which operates stably with use of a transistor having stable electric characteristics. In manufacture of a display device using transistors in which an oxide semiconductor layer is used for a channel formation region, a gate electrode is further provided over at least a transistor which is applied to a driver circuit. In manufacture of a transistor in which an oxide semiconductor layer is used for a channel formation region, the oxide semiconductor layer is subjected to heat treatment so as to be dehydrated or dehydrogenated; thus, impurities such as moisture existing in an interface between the oxide semiconductor layer and the gate insulating layer provided below and in contact with the oxide semiconductor layer and an interface between the oxide semiconductor layer and a protective insulating layer provided on and in contact with the oxide semiconductor layer can be reduced.