公开(公告)号：US20230402469A1

公开(公告)日：2023-12-14

申请号：US18238610

申请日：2023-08-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Jun KOYAMA ,  Kiyoshi KATO

IPC: H01L27/12 ,  H10B10/00 ,  H01L29/786 ,  H10B41/30 ,  H01L27/118 ,  H10B12/00 ,  H01L29/24 ,  H01L21/84 ,  H10B41/70 ,  H10B41/00

CPC classification number: H01L27/1255 ,  H10B10/125 ,  H01L29/7869 ,  H10B41/30 ,  H01L27/11803 ,  H01L27/1225 ,  H10B12/30 ,  H10B10/00 ,  H10B12/00 ,  H01L29/24 ,  H01L21/84 ,  H10B12/05 ,  H10B41/70 ,  H10B41/00 ,  G11C16/26

Abstract: An object of the present invention is to provide a semiconductor device having a novel structure in which in a data storing time, stored data can be stored even when power is not supplied, and there is no limitation on the number of writing. A semiconductor device includes a first transistor including a first source electrode and a first drain electrode; a first channel formation region for which an oxide semiconductor material is used and to which the first source electrode and the first drain electrode are electrically connected; a first gate insulating layer over the first channel formation region; and a first gate electrode over the first gate insulating layer. One of the first source electrode and the first drain electrode of the first transistor and one electrode of a capacitor are electrically connected to each other.

公开(公告)号：US20230402084A1

公开(公告)日：2023-12-14

申请号：US18233349

申请日：2023-08-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Hajime KIMURA ,  Atsushi MIYAGUCHI ,  Tatsunori INOUE

IPC: G11C11/405 ,  G06F12/0893 ,  H01L27/12 ,  H10B12/00

CPC classification number: G11C11/405 ,  G06F12/0893 ,  H01L27/1225 ,  H10B12/00

Abstract: A semiconductor device in which a memory region at each level of a memory device can be changed is provided. The semiconductor device includes a memory device including a first and a second memory circuit and a control circuit. The first memory circuit includes a first capacitor and a first transistor which has a function of holding charges held in the first capacitor. The second memory circuit includes a second transistor, a second capacitor which is electrically connected to a gate of the second transistor, and a third transistor which has a function of holding charges held in the second capacitor. The first and the third transistors each have a semiconductor layer including an oxide semiconductor, a gate, and a back gate. The voltage applied to the back gate of the first or the third transistor is adjusted, whereby the memory region of each of the first and the second memory circuit is changed.

公开(公告)号：US20230389262A1

公开(公告)日：2023-11-30

申请号：US18233172

申请日：2023-08-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Hajime KIMURA ,  Takayuki IKEDA ,  Kiyoshi KATO ,  Yuta ENDO ,  Junpei SUGAO

IPC: H10B12/00 ,  G11C5/02 ,  G11C11/403 ,  G11C11/409 ,  H01L29/24

CPC classification number: H10B12/00 ,  G11C5/02 ,  G11C11/403 ,  G11C11/409 ,  H01L29/24

Abstract: A semiconductor device with a large storage capacity per unit area is provided.
A semiconductor device includes a memory cell. The memory cell includes a first conductor; a first insulator over the first conductor; a first oxide over the first insulator and including a first region, a second region, and a third region positioned between the first region and the second region; a second insulator over the first oxide; a second conductor over the second insulator; a third insulator positioned in contact with a side surface of the first region; and a second oxide positioned on the side surface of the first region, with the third insulator therebetween. The first region includes a region overlapping the first conductor. The third region includes a region overlapped by the second conductor. The first region and the second region have a lower resistance than the third region.

公开(公告)号：US20230260556A1

公开(公告)日：2023-08-17

申请号：US18138196

申请日：2023-04-24

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tomoaki ATSUMI ,  Kiyoshi KATO ,  Tatsuya ONUKI ,  Shunpei YAMAZAKI

IPC: G11C7/04 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/12 ,  H01L29/221 ,  H10B12/00

CPC classification number: G11C7/04 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/1225 ,  H01L29/221 ,  H10B12/00

Abstract: A semiconductor device with a high on-state current and high operating speed is provided. The semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate, and the first gate and the second gate include a region where they overlap each other with a semiconductor layer therebetween. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor has a function of obtaining temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage. The first circuit applies the control voltage to the second gate.

公开(公告)号：US20220093141A1

公开(公告)日：2022-03-24

申请号：US17540314

申请日：2021-12-02

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tomoaki ATSUMI ,  Kiyoshi KATO ,  Tatsuya ONUKI ,  Shunpei YAMAZAKI

IPC: G11C7/04 ,  G11C5/14 ,  G11C11/4074 ,  H01L27/108 ,  H01L27/12 ,  H01L29/221

Abstract: A semiconductor device with a high on-state current and high operating speed is provided. The semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate, and the first gate and the second gate include a region where they overlap each other with a semiconductor layer therebetween. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor has a function of obtaining temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage. The first circuit applies the control voltage to the second gate.

公开(公告)号：US20210343329A1

公开(公告)日：2021-11-04

申请号：US17377757

申请日：2021-07-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya ONUKI ,  Takanori MATSUZAKI ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

IPC: G11C11/4091 ,  G11C5/02 ,  G11C5/06 ,  H01L27/108

Abstract: A memory device in which bit line parasitic capacitance is reduced is provided. The memory device includes a sense amplifier electrically connected to a bit line and a memory cell array stacked over the sense amplifier. The memory cell array includes a plurality of memory cells. The plurality of memory cells are each electrically connected to a bit line. A portion for leading the bit lines is not provided in the memory cell array. Thus, the bit line can be shortened and the bit line parasitic capacitance is reduced.

公开(公告)号：US20210312970A1

公开(公告)日：2021-10-07

申请号：US17298964

申请日：2019-11-20

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tatsuya ONUKI ,  Kiyoshi KATO ,  Shunpei YAMAZAKI

IPC: G11C11/405 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786 ,  G11C11/4096

Abstract: A semiconductor device having a novel structure is provided. The semiconductor device includes a first transistor one of a source and a drain of which is electrically connected to a first wiring for reading data; a second transistor one of a source and a drain of which is electrically connected to a gate of the first transistor and the other of the source and the drain of which is electrically connected to a second wiring for writing the data; and a third transistor one of a source and a drain of which is electrically connected to the gate of the first transistor and the other of the source and the drain of which is electrically connected to a capacitor for retaining electric charge corresponding to the data, and the third transistor includes a metal oxide in a channel formation region.

公开(公告)号：US20210135674A1

公开(公告)日：2021-05-06

申请号：US17150859

申请日：2021-01-15

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi FUJITA ,  Yutaka SHIONOIRI ,  Kiyoshi KATO ,  Hidetomo KOBAYASHI

IPC: H03K19/17728 ,  H03K19/173 ,  H03K19/17772 ,  H03K19/17758

Abstract: An object is to provide a semiconductor device that can maintain the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units even after supply of power supply voltage is stopped. Another object is to provide a semiconductor device in which the connection relation between logic circuit units or the circuit configuration of each of the logic circuit units can be changed at high speed. In a reconfigurable circuit, an oxide semiconductor is used for a semiconductor element that stores data on the circuit configuration, connection relation, or the like. Specifically, the oxide semiconductor is used for a channel formation region of the semiconductor element.

公开(公告)号：US20210134847A1

公开(公告)日：2021-05-06

申请号：US16616707

申请日：2018-05-25

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Tomoaki ATSUMI

IPC: H01L27/12 ,  H01L27/108

Abstract: A novel semiconductor device formed with single-polarity circuits using OS transistors is provided. Thus, connection between different layers in a memory circuit is unnecessary. This can reduce the number of connection portions and improve the flexibility of circuit layout and the reliability of the OS transistors. In particular, many memory cells are provided; thus, the memory cells are formed with single-polarity circuits, whereby the number of connection portions can be significantly reduced. Further, by providing a driver circuit in the same layer as the cell array, many wirings for connecting the driver circuit and the cell array can be prevented from being provided between layers, and the number of connection portions can be further reduced. An interposer provided with a plurality of integrated circuits can function as one electronic component.

公开(公告)号：US20210012816A1

公开(公告)日：2021-01-14

申请号：US16764955

申请日：2018-11-30

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Tomoaki ATSUMI ,  Kiyoshi KATO ,  Tatsuya ONUKI ,  Shunpei YAMAZAKI

IPC: G11C7/04 ,  G11C11/4074 ,  G11C5/14 ,  H01L27/108 ,  H01L27/12 ,  H01L29/221

Abstract: A semiconductor device with a high on-state current and high operating speed is provided. The semiconductor device includes a transistor and a first circuit. The transistor includes a first gate and a second gate, and the first gate and the second gate include a region where they overlap each other with a semiconductor layer therebetween. The first circuit includes a temperature sensor and a voltage control circuit. The temperature sensor has a function of obtaining temperature information and outputting the temperature information to the voltage control circuit. The voltage control circuit has a function of converting the temperature information into a control voltage. The first circuit applies the control voltage to the second gate.