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    HIGH-SPEED PHASE-ADJUSTED QUADRATURE DATA RATE (QDR) TRANSCEIVER AND METHOD THEREOF
    81.
    发明申请
    HIGH-SPEED PHASE-ADJUSTED QUADRATURE DATA RATE (QDR) TRANSCEIVER AND METHOD THEREOF 有权
    高速相位调整数据速率（QDR）收发器及其方法

    公开(公告)号：US20070206428A1

    公开(公告)日：2007-09-06

    申请号：US11612800

    申请日：2006-12-19

    申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Sang-Woong Shin ,  Ho-Young Song

    发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Kwang-II Park ,  Sang-Woong Shin ,  Ho-Young Song

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    摘要： A high-speed double or quadrature data rate interface semiconductor device and a method thereof are provided. A transmitter (e.g., a data transmitting semiconductor device) for high-speed data transmission transmits a first strobe signal and a second strobe signal, which have a phase difference of 90 degrees there-between, a first group (byte of) data, and a second group (byte of) data. The transmitter adjusts the phase of at least one of the first and second strobe signals based on phase-error information fed back from a receiver and then transmits the phase-adjusted strobe signal to the receiver. The receiver receives the first and second strobe signals from the transmitter and receives the first group (byte of) data and the second group (byte of) data using the first and second strobe signals. The receiver does not require a phase-locked loop (PLL) or a delay-locked loop (DLL), thereby decreasing the circuit area and power consumption of the receiver. In addition, since source synchronization is realized using a strobe signal, phase noise can be efficiently removed.

    摘要翻译： 提供了一种高速双倍或正交数据速率接口半导体器件及其方法。 用于高速数据传输的发射机（例如，数据传输半导体器件）发送第一选通信号和第二选通信号，第一选通信号和第二选通信号之间具有90度的相位差，第一组（字节）数据和 第二组（字节）数据。 发射机基于从接收机反馈的相位误差信息来调节第一和第二选通信号中的至少一个的相位，然后将相位调整的选通信号发送到接收机。 接收机从发送器接收第一和第二选通信号，并使用第一和第二选通信号接收数据的第一组（字节）和第二组（字节）数据。 接收机不需要锁相环（PLL）或延迟锁定环（DLL），从而减少接收机的电路面积和功耗。 此外，由于使用选通信号实现源同步，因此可以有效地去除相位噪声。

    Input buffer having a stabilized operating point and an associated method
    82.
    发明授权
    Input buffer having a stabilized operating point and an associated method 失效
    输入缓冲器具有稳定的工作点和相关联的方法

    公开(公告)号：US07205799B2

    公开(公告)日：2007-04-17

    申请号：US11225915

    申请日：2005-09-13

    申请人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-II Park ,  Sang-Joon Hwang ,  Ho-Young Song ,  Ho-Kyong Lee ,  Woo-Jin Lee

    发明人： Hyun-Jin Kim ,  Seong-Jin Jang ,  Kwang-II Park ,  Sang-Joon Hwang ,  Ho-Young Song ,  Ho-Kyong Lee ,  Woo-Jin Lee

    IPC分类号： H03K3/00

    CPC分类号： H03F3/45

    摘要： We describe an input buffer having a stabilized operating point and an associated method. An input buffer may include a first differential amplifying unit to generate a first output signal having a first operating point and a second differential amplifying unit to generate a second output signal having a second operating point. An output control circuit varies respective weights of the first and second output signals responsive to an output control signal. The first differential amplifying unit may operate responsive to a reference voltage and an input voltage signal. The second differential amplifying unit may operate responsive to the reference voltage and the input voltage signal. The first operating point may be relatively higher than the second operating point.

    摘要翻译： 我们描述具有稳定的工作点和相关方法的输入缓冲器。 输入缓冲器可以包括第一差分放大单元，用于产生具有第一工作点的第一输出信号和第二差分放大单元，以产生具有第二工作点的第二输出信号。 响应于输出控制信号，输出控制电路改变第一和第二输出信号的各个权重。 第一差分放大单元可以响应于参考电压和输入电压信号而进行操作。 第二差分放大单元可以响应于参考电压和输入电压信号而工作。 第一工作点可以相对高于第二工作点。

    Semiconductor memory device and data read and write method of the same
    84.
    发明申请
    Semiconductor memory device and data read and write method of the same 失效
    半导体存储器件和数据读写方法相同

    公开(公告)号：US20050174858A1

    公开(公告)日：2005-08-11

    申请号：US11024272

    申请日：2004-12-27

    申请人： Seong-Jin Jang

    发明人： Seong-Jin Jang

    IPC分类号： G11C11/407 ,  G11C5/00 ,  G11C7/22 ,  G11C11/40 ,  G11C11/409

    CPC分类号： G11C7/22 ,  G11C7/1066

    摘要： A semiconductor memory device includes a memory cell array to store data; a data input portion to output data to the memory cell array in response to a write control signal; a data output portion to output data from the memory cell array in response to a read control signal; a data I/O gate to transmit data outputted from the data input portion to the memory cell array in response to the write control signal, and transmitting data outputted from the memory cell array to the data output portion in response to the read control signal; and a data I/O controller to generate the read control signal and the write control signal having a smaller minimum cycle time than a minimum cycle time of the read control signal. The semiconductor memory device has an improved operation performance compared to one having a low operation frequency within an operable frequency range.

    摘要翻译： 半导体存储器件包括用于存储数据的存储单元阵列; 数据输入部分，用于响应写控制信号将数据输出到存储单元阵列; 数据输出部分，用于响应于读取控制信号从存储单元阵列输出数据; 数据I / O门，用于响应于写控制信号将从数据输入部分输出的数据发送到存储单元阵列;以及响应于读控制信号将从存储单元阵列输出的数据发送到数据输出部分; 以及数据I / O控制器，用于产生具有比所读取的控制信号的最小周期时间更小的最小周期时间的读取控制信号和写入控制信号。 与在可操作频率范围内具有低工作频率的半导体存储器件相比，具有改进的操作性能。

    Voltage generating circuit and method
    85.
    发明授权
    Voltage generating circuit and method 有权
    电压发生电路及方法

    公开(公告)号：US06850110B2

    公开(公告)日：2005-02-01

    申请号：US10108276

    申请日：2002-03-27

    申请人： Seong-Jin Jang

    发明人： Seong-Jin Jang

    IPC分类号： G11C5/14 ,  H02M3/07 ,  G06F7/64

    CPC分类号： H02M3/073 ,  H02M2003/075

    摘要： A voltage generating circuit and method thereof for preventing a current from flowing from a voltage generating node to a pumping node in transiting of the circuit from an active operation to a pre-charge operation are provided. The voltage generating circuit comprises a pre-charge circuit for pre-charging a pumping node and a voltage transmitting control node during a pre-charge operation; a voltage pumping circuit for pumping a signal at the pumping node during an active operation; a voltage transmitting circuit for transmitting the signal from the pumping node to a voltage generating node in response to a signal at the voltage transmitting control node during the active operation; and a countercurrent preventing circuit for varying the signal at the voltage transmitting control node based on the signal at the pumping node during the pre-charge operation and for preventing a current from flowing between the pumping node and the voltage transmitting control node during the active operation.

    摘要翻译： 提供一种电压产生电路及其方法，用于防止电流从电压产生节点流向泵送节点，以将电路从有源操作转移到预充电操作。 电压产生电路包括用于在预充电操作期间预充电泵浦节点和电压发送控制节点的预充电电路; 用于在主动操作期间泵送泵送节点处的信号的电压泵浦电路; 电压发送电路，用于在主动操作期间响应于电压发送控制节点处的信号将信号从泵送节点发送到电压产生节点; 以及逆流防止电路，用于在预充电操作期间基于泵送节点处的信号来改变电压发送控制节点处的信号，并且用于在主动操作期间防止在泵送节点和电压发送控制节点之间流动的电流 。

    Method and memory system having mode selection between dual data strobe mode and single data strobe mode with inversion
    87.
    发明申请
    Method and memory system having mode selection between dual data strobe mode and single data strobe mode with inversion 有权
    方法和存储器系统具有双数据选通模式和单反数据选通模式之间的模式选择

    公开(公告)号：US20050005053A1

    公开(公告)日：2005-01-06

    申请号：US10733413

    申请日：2003-12-12

    申请人： Seong-Jin Jang

    发明人： Seong-Jin Jang

    IPC分类号： G11C11/407 ,  G06F12/00 ,  G11C7/00 ,  G11C7/10 ,  G11C11/401

    CPC分类号： G11C7/1006 ,  G11C7/1045 ,  G11C7/1075

    摘要： A memory system and a method of reading and writing data to a memory device selectively operate in both a single DQS mode with data inversion, and in a dual DQS mode. The device and method employ data strobe mode changing means for selectively changing operation of the memory device between a first data strobe mode and a second data strobe mode.

    摘要翻译： 存储器系统和将数据读取和写入到存储器件的方法选择性地在具有数据反转的单个DQS模式中操作，并且以双DQS模式操作。 该装置和方法采用数据选通模式改变装置，用于在第一数据选通模式和第二数据选通模式之间选择性地改变存储装置的操作。

    Voltage and time control circuits
    88.
    发明授权
    Voltage and time control circuits 有权
    电压和时间控制电路

    公开(公告)号：US06788132B2

    公开(公告)日：2004-09-07

    申请号：US10147553

    申请日：2002-05-17

    申请人： Kyu-Nam Lim ,  Sang-Seok Kang ,  Seong-Jin Jang

    发明人： Kyu-Nam Lim ,  Sang-Seok Kang ,  Seong-Jin Jang

    IPC分类号： G05F302

    CPC分类号： G05F1/465

    摘要： Integrated circuits are provided that include a voltage control circuit that is configured to adjust a circuit voltage that is outside a predetermined circuit voltage specification to within the predetermined circuit voltage specification so that the integrated circuit device is no longer defective. Integrated circuits are also provided that include a signal time delay control circuit that is configured to adjust a circuit delay time that is outside a predetermined circuit delay time specification to within the predetermined circuit delay time specification so that the integrated circuit device is no longer defective. Corresponding methods of operation are also provided.

    摘要翻译： 提供了集成电路，其包括电压控制电路，其被配置为将预定电路电压规范之外的电路电压调整到预定电路电压规范内，使得集成电路器件不再有缺陷。 还提供了集成电路，其包括信号时间延迟控制电路，其被配置为将预定电路延迟时间规范之外的电路延迟时间调整到预定电路延迟时间规范内，使得集成电路装置不再有缺陷。 还提供了相应的操作方法。

    Semiconductor device, a parallel interface system and methods thereof
    89.
    发明授权
    Semiconductor device, a parallel interface system and methods thereof 有权
    半导体器件，并行接口系统及其方法

    公开(公告)号：US08780668B2

    公开(公告)日：2014-07-15

    申请号：US13483719

    申请日：2012-05-30

    申请人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

    发明人： Seung-Jun Bae ,  Seong-Jin Jang ,  Beom-Sig Cho

    IPC分类号： G11C8/00

    CPC分类号： G11C7/22 ,  H03K19/0966 ,  H04L7/0008 ,  H04L7/033 ,  H04L7/10

    摘要： A memory device includes a clock receiving block, a data transceiver block, a phase detection block, and a phase information transmitter. The clock receiving block is configured to receive a clock signal from a memory controller through a clock signal line and generate a data sampling clock signal and an edge sampling clock signal. The data transceiver block is configured to receive a data signal from the memory controller through a data signal line. The phase detection block is configured to generate phase information in response to the data sampling clock signal, the edge sampling clock signal and the data signal. The phase information transmitter is configured to transmit the phase information to the memory controller through a phase information signal line that is separate from the data signal line.

    摘要翻译： 存储器件包括时钟接收块，数据收发器块，相位检测块和相位信息发送器。 时钟接收块被配置为通过时钟信号线从存储器控制器接收时钟信号，并生成数据采样时钟信号和边沿采样时钟信号。 数据收发器模块被配置为通过数据信号线从存储器控制器接收数据信号。 相位检测块被配置为响应于数据采样时钟信号，边沿采样时钟信号和数据信号而产生相位信息。 相位信息发送器被配置为通过与数据信号线分离的相位信息信号线将相位信息发送到存储器控制器。