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88 条记录 (耗时 0.039 秒)

    Apparatus for aligning input data in semiconductor memory device
    81.
    发明授权
    Apparatus for aligning input data in semiconductor memory device 失效
    用于对准半导体存储器件中的输入数据的装置

    公开(公告)号：US07975162B2

    公开(公告)日：2011-07-05

    申请号：US11986917

    申请日：2007-11-27

    申请人： Kyoung-Ho Kim ,  Kwang-Il Park

    发明人： Kyoung-Ho Kim ,  Kwang-Il Park

    IPC分类号： G06F1/00 ,  G11C7/00 ,  G11C8/00

    CPC分类号： G11C7/1078 ,  G11C7/1006 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C2207/107

    摘要： An apparatus for aligning input data in a semiconductor device includes at least one alignment block and a decision block. The at least one alignment block is for aligning serial input data into groups of parallel data synchronized to at least one divided data strobe signal for increasing margin between the maximum and minimum tDQSS values. The decision block is for selecting one of the groups of parallel data as valid data in response to synchronization information generated for removing any invalid data in the serial input data resulting from a write gap.

    摘要翻译： 用于对准半导体器件中的输入数据的装置包括至少一个对准块和判定块。 所述至少一个对准块用于将串行输入数据对准到与至少一个分割数据选通信号同步的并行数据组，以增加最大和最小tDQSS值之间的余量。 所述决定块用于响应于产生的同步信息来选择并行数据组中的一个作为有效数据，以消除由写入间隙产生的串行输入数据中的任何无效数据。

    Apparatus and method for correcting duty cycle of clock signal
    83.
    发明申请
    Apparatus and method for correcting duty cycle of clock signal 审中-公开
    用于校正时钟信号占空比的装置和方法

    公开(公告)号：US20080169855A1

    公开(公告)日：2008-07-17

    申请号：US11809971

    申请日：2007-06-04

    申请人： Won-Hwa Shin ,  Sung-Man Park ,  Kwang-Il Park

    发明人： Won-Hwa Shin ,  Sung-Man Park ,  Kwang-Il Park

    IPC分类号： H03K3/017

    CPC分类号： H03K5/1565

    摘要： An apparatus for correcting a duty cycle of an input clock signal to generate a digitally corrected clock signal includes a duty cycle detector, an analog duty cycle correcting unit, and a digital duty cycle correcting unit. The duty cycle detector generates a duty cycle signal indicating a respective duty cycle of the digitally corrected clock signal. The analog duty cycle correcting unit adjusts a current flowing through a node to adjust the respective duty cycle of the input clock signal for generating an analog corrected clock signal at the node. The digital duty cycle correcting unit adjusts the respective duty cycle of the analog corrected clock signal according to the duty cycle signal for generating the digitally corrected clock signal.

    摘要翻译： 用于校正输入时钟信号的占空比以产生经数字校正的时钟信号的装置包括占空比检测器，模拟占空比校正单元和数字占空比校正单元。 占空比检测器产生指示数字校正的时钟信号的相应占空比的占空比信号。 模拟占空比校正单元调节流过节点的电流，以调整输入时钟信号的相应占空比，以在节点处产生模拟校正时钟信号。 数字占空比校正单元根据用于产生经数字校正的时钟信号的占空比信号来调整模拟校正时钟信号的相应占空比。

    Delay locked loop, semiconductor memory device including the same, and method of generating delay clock signals
    84.
    发明申请
    Delay locked loop, semiconductor memory device including the same, and method of generating delay clock signals 有权
    延迟锁定环路，包括其的半导体存储器件以及产生延迟时钟信号的方法

    公开(公告)号：US20080012615A1

    公开(公告)日：2008-01-17

    申请号：US11819070

    申请日：2007-06-25

    申请人： Kwang-Il Park

    发明人： Kwang-Il Park

    IPC分类号： H03L7/06 ,  G11C7/00 ,  H03H11/26

    CPC分类号： G11C7/22 ,  G11C7/222 ,  H03H11/265 ,  H03L7/07 ,  H03L7/0814

    摘要： A delay locked loop may include a period locked loop portion. The period locked loop portion may include a delay. The delay may include an even number of delay cells dependently connected in the form of a ring configured to generate an even number of delay clock signals. Transition of at least one delay clock signal of the even number of delay clock signals is configured to be controlled in response to an activated one first selecting signal of an even number of first selecting signals, and transition of the remaining clock signals is configured to occur in response to the at least one delay clock signal.

    摘要翻译： 延迟锁定环路可以包括周期锁定环路部分。 周期锁定环路部分可以包括延迟。 该延迟可以包括以环形式依赖地连接的偶数个延迟单元，其被配置为产生偶数个延迟时钟信号。 偶数个延迟时钟信号的至少一个延迟时钟信号的转换被配置为响应于激活的偶数个第一选择信号的一个第一选择信号被控制，并且剩余时钟信号的转换被配置为发生 响应于所述至少一个延迟时钟信号。

    Duty cycle correction circuit and a method for duty cycle correction in a delay locked loop using an inversion locking scheme
    85.
    发明授权
    Duty cycle correction circuit and a method for duty cycle correction in a delay locked loop using an inversion locking scheme 失效
    使用倒置锁定方案的延迟锁定环中的占空比校正电路和占空比校正方法

    公开(公告)号：US07183824B2

    公开(公告)日：2007-02-27

    申请号：US11235646

    申请日：2005-09-26

    申请人： Kwang-Il Park ,  Hyun-Dong Kim ,  Mi-Jin Lee

    发明人： Kwang-Il Park ,  Hyun-Dong Kim ,  Mi-Jin Lee

    IPC分类号： H03K3/017

    CPC分类号： G11C11/15 ,  G11C11/5607 ,  H03K5/133 ,  H03K5/1565 ,  H03L7/0812 ,  H03L7/0891

    摘要： Provided are a duty cycle correction circuit and method for duty cycle correction in a delay locked loop using an inversion locking scheme. The duty cycle correction circuit comprises: a correction unit exchanging and receiving a first duty correction signal and a second duty correction signal and selecting and receiving one of an input clock signal and an inversion signal of the input clock signal in response to an inversion locking signal, and correcting the duty cycle of the received input clock signal or inversion signal of the input clock signal in response to the first and second duty correction signals; a buffer buffering an output signal of the correction unit and outputting the buffered signal as a corrected clock signal; and a duty detector selecting and receiving one of the corrected clock signal and an inversion signal of the corrected clock signal in response to the inversion locking signal, and generating the first and second duty correction signals using the received corrected clock signal or inversion signal of the corrected clock signal.

    摘要翻译： 提供了一种使用反转锁定方案的延迟锁定环中的占空比校正电路和方法。 占空比校正电路包括：校正单元，响应于反相锁定信号，交换和接收第一占空比校正信号和第二占空比校正信号，并选择和接收输入时钟信号和反相信号之一 并且响应于第一和第二占空比校正信号，校正接收到的输入时钟信号的占空比或输入时钟信号的反相信号; 缓冲校正单元的输出信号并输出​​缓冲信号作为校正时钟信号的缓冲器; 以及负载检测器，其响应于所述反相锁定信号选择和接收所述经校正的时钟信号中的一个和所述经校正的时钟信号的反相信号，以及使用所接收的校正时钟信号或所述反相信号产生所述第一和第二占空比校正信号 校正时钟信号。

    Fixed offset digital-to-analog conversion device and method
    86.
    发明申请
    Fixed offset digital-to-analog conversion device and method 有权

    公开(公告)号：US20060028366A1

    公开(公告)日：2006-02-09

    申请号：US11118229

    申请日：2005-04-28

    申请人： Kwang-Il Park

    发明人： Kwang-Il Park

    IPC分类号： H03M1/66

    CPC分类号： H03M1/0607 ,  H03M1/0675 ,  H03M1/0682 ,  H03M1/742

    摘要： I describe and claim an improved digital-to-analog conversion device and method. The device comprises a current supply circuit to generate a plurality of control currents responsive to a plurality of digital signals. An input voltage generating circuit is adapted to generate a plurality of input voltages responsive to the digital signals and the control currents. And a plurality of operational amplifiers is adapted to output a plurality of analog signals responsive to the input voltages.

    Squelch circuit to create a squelch waveform for USB 2.0
    88.
    发明授权
    Squelch circuit to create a squelch waveform for USB 2.0 失效

    公开(公告)号：US06653892B2

    公开(公告)日：2003-11-25

    申请号：US10226057

    申请日：2002-08-22

    申请人： Kwang-Il Park

    发明人： Kwang-Il Park

    IPC分类号： G06G712

    CPC分类号： G06F13/4077

    摘要： Disclosed is a squelch circuit capable of detecting whether an absolute value of input voltage is over a specific voltage difference or not. The squelch circuit according to the present invention comprises: a first differential amplifier for receiving first and second input signals, for sensing a first voltage difference between the first and second input signals and for outputting a first sensing signal when the first voltage difference is over a specific positive value; a second differential amplifier for receiving the first and second input signals, for sensing a second voltage difference between the first and second input signals and for outputting a second sensing signal when the second voltage difference is over a specific negative value; an offset current determining unit coupled to the first and second differential amplifiers for respectively controlling first and second offset currents of the first and second differential amplifiers to determine the specific positive and negative values; and an output unit for outputting a squelch signal in response to the first and second sensing signals.