公开(公告)号：US06486078B1

公开(公告)日：2002-11-26

申请号：US09643531

申请日：2000-08-22

申请人： Bharath Rangarajan ,  Ramkumar Subramanian ,  Bhanwar Singh

发明人： Bharath Rangarajan ,  Ramkumar Subramanian ,  Bhanwar Singh

IPC分类号： H01L2131

CPC分类号： H01L21/0212 ,  H01L21/02203 ,  H01L21/02282 ,  H01L21/02343 ,  H01L21/31695

摘要： One aspect of the present invention relates to a method of forming a low k material layer on a semiconductor substrate, involving the steps of depositing a mixture containing a low k material and a casting solvent on the semiconductor substrate; optionally contacting the mixture with a transition solvent whereby the casting solvent is removed from the mixture to form a second mixture containing the low k material and the transition solvent; contacting the second mixture with a supercritical fluid whereby the transition solvent is removed from the second mixture; and permitting the supercritical fluid to evaporate thereby forming the low k material layer.

摘要翻译： 本发明的一个方面涉及在半导体衬底上形成低k材料层的方法，包括在半导体衬底上沉积含有低k材料和浇铸溶剂的混合物的步骤; 任选地将混合物与过渡溶剂接触，由此从混合物中除去浇注溶剂以形成含有低k材料和过渡溶剂的第二混合物; 使所述第二混合物与超临界流体接触，由此从所述第二混合物中除去所述过渡溶剂; 并允许超临界流体蒸发，从而形成低k材料层。

公开(公告)号：US06459482B1

公开(公告)日：2002-10-01

申请号：US09729294

申请日：2000-12-04

申请人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Michael K. Templeton ,  Sanjay K. Yedur ,  Bryan K. Choo

发明人： Bhanwar Singh ,  Ramkumar Subramanian ,  Khoi A. Phan ,  Bharath Rangarajan ,  Michael K. Templeton ,  Sanjay K. Yedur ,  Bryan K. Choo

IPC分类号： G01J110

CPC分类号： H01J37/28 ,  H01J2237/2826

摘要： The present invention provides SEM systems, SEM calibration standards, and SEM calibration methods that improved accuracy in critical dimension measurements. The calibration standards have features formed with an amorphous material such as amorphous silicon. Amorphous materials lack the crystal grain structure of materials such as polysilicon and are capable of providing sharper edged features and higher accuracy patterns than grained materials. The amorphous material can be bound to a silicon wafer substrate through an intermediate layer of material, such as silicon dioxide. Where the intermediate layer is insulating material, as is silicon dioxide, the intermediate layer may be patterned with gaps to provide for electrical communication between the amorphous silicon and the silicon wafer. Charges imparted to the amorphous silicon during electron beam scanning may thereby drain to the silicon wafer rather than accumulating to a level where they would distort the electron beam.

摘要翻译： 本发明提供SEM系统，SEM校准标准和SEM校准方法，提高了临界尺寸测量的精度。 校准标准品具有非晶体材料如非晶硅形成的特征。 无定形材料缺乏诸如多晶硅的材料的晶粒结构，并且能够提供比颗粒材料更尖锐的边缘特征和更高精度的图案。 非晶材料可以通过诸如二氧化硅的材料的中间层与硅晶片衬底结合。 在中间层是绝缘材料的情况下，如二氧化硅那样，中间层可以用间隙图案化以提供非晶硅和硅晶片之间的电连通。 因此，在电子束扫描期间赋予非晶硅的电荷可以从而被排出到硅晶片，而不是积聚到它们会使电子束变形的水平。

公开(公告)号：US06452161B1

公开(公告)日：2002-09-17

申请号：US09536529

申请日：2000-03-28

申请人： Sanjay K. Yedur ,  Bhanwar Singh ,  Bryan K. Choo ,  Carmen L. Morales

发明人： Sanjay K. Yedur ,  Bhanwar Singh ,  Bryan K. Choo ,  Carmen L. Morales

IPC分类号： H01J314

CPC分类号： G01Q30/02 ,  G01Q70/02 ,  Y10S977/868

摘要： A measuring system and apparatus is provided in which a scanning probe microscope includes a high resolution optical sensor adapted to view a portion of a workpiece beneath the scanning probe tip. Also provided is a scanning tip assembly with a cantilever/tip assembly and an optical sensor associated with a cantilever assembly. The optical sensor may comprise a charge coupled device or other solid state camera and may be fabricated on the cantilever and/or the tip. In addition, a scanning tip assembly is provided for a scanning probe microscope having an optical fiber adapted to receive reflected light from the at least a portion of the workpiece. The scanning tip may be employed in an AFM or other scanning probe microscope, thereby providing simultaneous viewing and scanning of a workpiece surface. Also provided is a measuring apparatus comprising a scanning probe microscope having an optical fiber adapted to receive reflected light from a feature of a workpiece, and a camera connected to the optical fiber to provide a visual image based on the reflected light from the feature of the workpiece.

摘要翻译： 提供了一种测量系统和装置，其中扫描探针显微镜包括适于在扫描探针尖端下方观察工件的一部分的高分辨率光学传感器。 还提供了具有悬臂/尖端组件和与悬臂组件相关联的光学传感器的扫描末端组件。 光学传感器可以包括电荷耦合器件或其他固态照相机，并且可以制造在悬臂和/或尖端上。 此外，为扫描探针显微镜提供扫描头组件，其具有适于接收来自工件的至少一部分的反射光的光纤。 扫描尖端可以用在AFM或其他扫描探针显微镜中，从而提供对工件表面的同时观察和扫描。 还提供了一种包括扫描探针显微镜的测量装置，该扫描探针显微镜具有适于接收来自工件特征的反射光的光纤，以及连接到光纤的照相机，以基于来自该特征的反射光提供视觉图像 工件。

公开(公告)号：US06451621B1

公开(公告)日：2002-09-17

申请号：US10050732

申请日：2002-01-16

申请人： Bharath Rangarajan ,  Bhanwar Singh ,  Ramkumar Subramanian

发明人： Bharath Rangarajan ,  Bhanwar Singh ,  Ramkumar Subramanian

IPC分类号： H01L2166

CPC分类号： H01L22/12

摘要： The present invention provides systems and methods wherein scatterometry is used to control an implant processes, such as an angled implant process. According to the invention, data relating to resist dimensions is obtained by scatterometry prior to an the implant process. The data is used to determine whether a resist is suitable for an implant process and/or determine an appropriate condition, such as an angle of implant or implantation dose, for an implant process.

摘要翻译： 本发明提供了系统和方法，其中使用散射法来控制植入过程，例如成角度的植入过程。 根据本发明，与抗蚀剂尺寸相关的数据通过在植入工艺之前的散射测量获得。 该数据用于确定抗蚀剂是否适合于植入过程，和/或确定用于植入过程的适当条件，例如植入角度或植入剂量。

公开(公告)号：US06445072B1

公开(公告)日：2002-09-03

申请号：US09617158

申请日：2000-07-17

申请人： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton ,  Bharath Rangarajan

发明人： Ramkumar Subramanian ,  Bhanwar Singh ,  Michael K. Templeton ,  Bharath Rangarajan

IPC分类号： H01L214763

CPC分类号： H01L21/7682 ,  Y10S977/897

摘要： One aspect of the present invention relates to a method of forming an innerlayer dielectric, involving the steps of providing a substrate having at least two metal lines thereon; providing a conformal insulation layer over the substrate and metal lines; forming a second insulation layer over the conformal insulation layer, the second insulation layer containing a void positioned between two metal lines; at least one of thinning and planarizing the second insulation layer; and forming a third insulation layer over the second insulation layer. Another aspect of the present invention relates to an innerlayer dielectric semiconductor structure, containing a semiconductor substrate having at least two metal lines thereon; a conformal insulation layer over the semiconductor substrate and metal lines, the conformal insulation layer having a substantially uniform thickness from about 250 Å to about 5,000 Å; a second insulation layer over the conformal insulation layer, the second insulation layer containing a void positioned between two metal lines; and a third insulation layer over the second insulation layer.

摘要翻译： 本发明的一个方面涉及一种形成内层电介质的方法，包括以下步骤：提供其上具有至少两条金属线的基底; 在衬底和金属线上提供保形绝缘层; 在所述保形绝缘层上形成第二绝缘层，所述第二绝缘层包含位于两条金属线之间的空隙; 将所述第二绝缘层变薄和平坦化的至少一个; 以及在所述第二绝缘层上形成第三绝缘层。 本发明的另一方面涉及一种内层电介质半导体结构，其包含其上具有至少两条金属线的半导体衬底; 半导体衬底和金属线上的共形绝缘层，保形绝缘层具有从大约至大约等于的大致均匀的厚度; 在保形绝缘层之上的第二绝缘层，所述第二绝缘层包含位于两个金属线之间的空隙; 以及在所述第二绝缘层上的第三绝缘层。

公开(公告)号：US06422918B1

公开(公告)日：2002-07-23

申请号：US09478118

申请日：2000-01-04

申请人： Steven Avanzino ,  Bhanwar Singh ,  Bharath Rangarajan ,  Alvin M. Dangca

发明人： Steven Avanzino ,  Bhanwar Singh ,  Bharath Rangarajan ,  Alvin M. Dangca

IPC分类号： B24B4900

CPC分类号： H01L21/0273 ,  G03F7/168 ,  G03F7/3021 ,  H01L21/31058

摘要： The present invention relates to a system for controllably removing photoresist. A CMP system is employed for polishing the photoresist. A non-abrasive polishing liquid adapted to react with the photoresist to sufficiently modify bonding in the photoresist is employed to facilitate surface layer removal of the photoresist by applied mechanical stress from the CMP system.

摘要翻译： 本发明涉及可控制地除去光致抗蚀剂的系统。 使用CMP系统来抛光光致抗蚀剂。 采用适于与光致抗蚀剂反应以充分改善光致抗蚀剂中的结合的非磨料抛光液，以便通过来自CMP系统的应力机械应力促进光致抗蚀剂的表面层去除。

公开(公告)号：US06413857B1

公开(公告)日：2002-07-02

申请号：US09824349

申请日：2001-04-02

申请人： Ramkumar Subramanian ,  Bharath Rangarajan ,  Bhanwar Singh

发明人： Ramkumar Subramanian ,  Bharath Rangarajan ,  Bhanwar Singh

IPC分类号： H01L214763

CPC分类号： H01L29/66772 ,  H01L21/743 ,  H01L21/84 ,  H01L29/78612 ,  H01L29/78645 ,  H01L29/78648

摘要： An SOI device structure is provided which facilitates mitigation of charge build up caused by floating body effects. A plurality of local interconnects are formed from a top insulating layer to a top silicon layer of the SOI device structure. A ground contact is then formed from the top insulating layer to a bottom substrate layer of the SOI device structure. The ground contact extends through the insulating layer, an isolation region and an oxide layer to the bottom substrate layer.

摘要翻译： 提供了SOI器件结构，其有助于减轻由浮体效应引起的电荷积累。 多个局部互连由SOI器件结构的顶部绝缘层到顶部硅层形成。 然后从顶部绝缘层到SOI器件结构的底部基底层形成接地触点。 接地触头延伸穿过绝缘层，隔离区域和氧化物层延伸到底部基底层。

公开(公告)号：US06358843B1

公开(公告)日：2002-03-19

申请号：US09824421

申请日：2001-04-02

申请人： Carl P. Babcock ,  Bhanwar Singh

发明人： Carl P. Babcock ,  Bhanwar Singh

IPC分类号： H01L214763

CPC分类号： G03F7/203 ,  H01L21/0274 ,  H01L21/31144 ,  H01L21/76802

摘要： A method of fabricating ultra small vias in insulating layers on a semiconductor substrate for an integrated circuit by a first exposure of a photoresist to line pattern with the semiconductor substrate in a first position and the exposure dosage being insufficient to develop the photoresist followed by a second overlapping exposure of the line pattern with the semiconductor substrate being in a position 90° from the first position and again being insufficient in exposure dosage to develop the photoresist, the overlapped line exposures creating via exposures of sufficient dosage to develop the photoresist, thereby creating a smaller via opening than with a single exposure.

摘要翻译： 一种在半导体衬底上用于集成电路的绝缘层中的超小通孔的制造方法，该方法是通过在第一位置首先将半导体衬底的光致抗蚀剂曝光到线图案，并且曝光剂量不足以显影光致抗蚀剂，然后是第二 线路图案与半导体衬底的重叠曝光处于距离第一位置90°的位置，并且曝光用量不足以显影光致抗蚀剂，通过曝光足够的剂量产生重叠的线暴露以显影光致抗蚀剂，由此产生 通过开口比单次曝光更小。

公开(公告)号：US06354133B1

公开(公告)日：2002-03-12

申请号：US09729293

申请日：2000-12-04

申请人： Sanjay K. Yedur ,  Bhanwar Singh ,  Bryan K. Choo ,  Michael K. Templeton ,  Ramkumar Subramanian

发明人： Sanjay K. Yedur ,  Bhanwar Singh ,  Bryan K. Choo ,  Michael K. Templeton ,  Ramkumar Subramanian

IPC分类号： G01B528

CPC分类号： G01Q40/02 ,  G01Q40/00 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/849 ,  Y10S977/85 ,  Y10S977/876 ,  Y10S977/901

摘要： The present invention provides systems, methods, and standards for calibrating nano-measuring devices. Calibration standards of the invention include carbon nanotubes and methods of the invention involve scanning carbon nanotubes using nano-scale measuring devices. The widths of the carbon nanotube calibration standards are known with a high degree of accuracy. The invention allows calibration of a wide variety of nano-scale measuring devices, taking into account many, and in some cases all, of the systematic errors that may affect a nano-scale measurement. The invention may be used to accurately calibrate line width, line height, and trench width measurements and may be used to precisely characterize both scanning probe microscope tips and electron microscope beams.

摘要翻译： 本发明提供了用于校准纳米测量装置的系统，方法和标准。 本发明的校准标准包括碳纳米管，本发明的方法涉及使用纳米级测量装置扫描碳纳米管。 碳纳米管校准标准品的宽度以高精度已知。 考虑到可能影响纳米尺度测量的许多系统误差以及在所有这些系统误差中，本发明允许校准各种各样的纳米尺度的测量装置。 本发明可以用于精确校准线宽，线高度和沟槽宽度测量，并且可以用于精确地表征扫描探针显微镜尖端和电子显微镜束。

公开(公告)号：US06352817B1

公开(公告)日：2002-03-05

申请号：US09422592

申请日：1999-10-21

申请人： Bharath Rangarajan ,  Bhanwar Singh ,  Steven Avanzino

发明人： Bharath Rangarajan ,  Bhanwar Singh ,  Steven Avanzino

IPC分类号： G03C500

CPC分类号： H01L21/0274 ,  G03F7/38

摘要： The present invention relates to a method for mitigating T-tops and/or stringers and/or crusts in a structure. A photoresist layer of the structure is exposed. The structure further includes an underlayer under the photoresist layer, and a substrate under the underlayer. A chemical mechanical polishing process is employed to remove a predetermined thickness of the photoresist layer. An underlayer etch is performed to remove select portions of the underlayer.

摘要翻译： 本发明涉及一种用于减轻结构中的T形顶和/或桁条和/或外壳的方法。 曝光该结构的光致抗蚀剂层。 该结构还包括光致抗蚀剂层下的底层和底层下的基底。 采用化学机械抛光工艺去除光致抗蚀剂层的预定厚度。 执行底层蚀刻以去除底层的选择部分。