公开(公告)号：US20240320154A1

公开(公告)日：2024-09-26

申请号：US18733125

申请日：2024-06-04

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen Bhoria

IPC: G06F12/0811 ,  G06F9/46 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/1081 ,  G06F12/14 ,  G06F21/79

CPC classification number: G06F12/0811 ,  G06F9/467 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/1081 ,  G06F12/1441 ,  G06F21/79

Abstract: An example system includes first and second level memories and first and second memory controllers respectively coupled thereto. The system also includes a shadow cache associated with the second level memory and coupled to the second memory controller, which is also coupled to the first memory controller. In response to a generated read operation that includes a secure code, the second memory controller determines whether an address of the read operation matches an address that is tagged in the shadow cache; and determine whether the secure code of the read operation matches a secure code of a cache line hit by the read operation. The second memory controller then performs one of two sets of additional operations, depending on whether or not the address of the read operation matches the address tagged in the shadow cache and whether or not the secure code of the read operation matches the secure code of the cache line.

公开(公告)号：US12038840B2

公开(公告)日：2024-07-16

申请号：US18334740

申请日：2023-06-14

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen Bhoria

IPC: G06F12/0811 ,  G06F9/46 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/1081 ,  G06F12/14 ,  G06F21/79 ,  G06F12/0864 ,  G06F12/128

CPC classification number: G06F12/0811 ,  G06F9/467 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/1081 ,  G06F12/1441 ,  G06F21/79

Abstract: In described examples, a coherent memory system includes a central processing unit (CPU), and first and second level caches, each with a cache controller. The CPU is arranged to execute program instructions to manipulate data in at least a first or second secure context. Each of the first and second caches stores a secure code for indicating the secure context by which data for a respective cache line is received. The first and second level caches maintain coherency in response to comparing the secure codes of respective lines of cache and executing a cache coherency operation in response. A requestor coupled to the second level cache may send a coherence read transaction to the second level cache controller, which upon an affirmative security check, generates a snoop read transaction and sends the same to the first level cache.

公开(公告)号：US11977491B2

公开(公告)日：2024-05-07

申请号：US18194708

申请日：2023-04-03

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Bipin Prasad Heremagalur Ramaprasad ,  David Matthew Thompson ,  Abhijeet Ashok Chachad ,  Hung Ong

IPC: G06F12/10 ,  G06F12/1045 ,  G06F15/78

CPC classification number: G06F12/1045 ,  G06F15/7807 ,  G06F2212/301 ,  G06F2212/50

Abstract: A system comprises a processor including a CPU core, first and second memory caches, and a memory controller subsystem. The memory controller subsystem speculatively determines a hit or miss condition of a virtual address in the first memory cache and speculatively translates the virtual address to a physical address. Associated with the hit or miss condition and the physical address, the memory controller subsystem configures a status to a valid state. Responsive to receipt of a first indication from the CPU core that no program instructions associated with the virtual address are needed, the memory controller subsystem reconfigures the status to an invalid state and, responsive to receipt of a second indication from the CPU core that a program instruction associated with the virtual address is needed, the memory controller subsystem reconfigures the status back to a valid state.

公开(公告)号：US11940918B2

公开(公告)日：2024-03-26

申请号：US18167921

申请日：2023-02-13

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  Kai Chirca ,  David Matthew Thompson

IPC: G06F12/00 ,  G06F1/14 ,  G06F9/54 ,  G06F12/0811 ,  G06F12/0842 ,  G06F12/0888

CPC classification number: G06F12/0842 ,  G06F1/14 ,  G06F9/544 ,  G06F12/0811 ,  G06F12/0888 ,  G06F2212/1016

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

公开(公告)号：US20230325314A1

公开(公告)日：2023-10-12

申请号：US18334740

申请日：2023-06-14

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen Bhoria

IPC: G06F12/0811 ,  G06F12/0817 ,  G06F9/46 ,  G06F21/79 ,  G06F12/1081 ,  G06F12/0831 ,  G06F12/14

CPC classification number: G06F12/0811 ,  G06F12/0828 ,  G06F9/467 ,  G06F21/79 ,  G06F12/1081 ,  G06F12/0831 ,  G06F12/1441

Abstract: In described examples, a coherent memory system includes a central processing unit (CPU), and first and second level caches, each with a cache controller. The CPU is arranged to execute program instructions to manipulate data in at least a first or second secure context. Each of the first and second caches stores a secure code for indicating the secure context by which data for a respective cache line is received. The first and second level caches maintain coherency in response to comparing the secure codes of respective lines of cache and executing a cache coherency operation in response. A requestor coupled to the second level cache may send a coherence read transaction to the second level cache controller, which upon an affirmative security check, generates a snoop read transaction and sends the same to the first level cache.

公开(公告)号：US11762683B2

公开(公告)日：2023-09-19

申请号：US17542573

申请日：2021-12-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/448 ,  G06F11/30 ,  G06F9/54 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0813 ,  G06F12/0817 ,  G06F9/30 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/16 ,  G06F12/0888 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0804 ,  G06F12/121

CPC classification number: G06F9/467 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/3867 ,  G06F9/4498 ,  G06F9/4881 ,  G06F9/544 ,  G06F11/3037 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/1668 ,  G06F12/0804 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/621

Abstract: A method includes receiving, by a level two (L2) controller, a write request for an address that is not allocated as a cache line in a L2 cache. The write request specifies write data. The method also includes generating, by the L2 controller, a read request for the address; reserving, by the L2 controller, an entry in a register file for read data returned in response to the read request; updating, by the L2 controller, a data field of the entry with the write data; updating, by the L2 controller, an enable field of the entry associated with the write data; and receiving, by the L2 controller, the read data and merging the read data into the data field of the entry.

公开(公告)号：US11740930B2

公开(公告)日：2023-08-29

申请号：US17713287

申请日：2022-04-05

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  Naveen Bhoria ,  David Matthew Thompson ,  Neelima Muralidharan

IPC: G06F9/46 ,  G06F9/48 ,  G06F9/448 ,  G06F11/30 ,  G06F9/54 ,  G06F12/0811 ,  G06F9/38 ,  G06F12/0813 ,  G06F12/0817 ,  G06F9/30 ,  G06F12/0871 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/16 ,  G06F12/0888 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0804 ,  G06F12/121

CPC classification number: G06F9/467 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/3867 ,  G06F9/4498 ,  G06F9/4881 ,  G06F9/544 ,  G06F11/3037 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0824 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0855 ,  G06F12/0871 ,  G06F12/0888 ,  G06F12/0891 ,  G06F12/12 ,  G06F13/1668 ,  G06F12/0804 ,  G06F12/121 ,  G06F2212/1016 ,  G06F2212/1044 ,  G06F2212/621

Abstract: A method includes receiving, by a L2 controller, a request to perform a global operation on a L2 cache and preventing new blocking transactions from entering a pipeline coupled to the L2 cache while permitting new non-blocking transactions to enter the pipeline. Blocking transactions include read transactions and non-victim write transactions. Non-blocking transactions include response transactions, snoop transactions, and victim transactions. The method further includes, in response to an indication that the pipeline does not contain any pending blocking transactions, preventing new snoop transactions from entering the pipeline while permitting new response transactions and victim transactions to enter the pipeline; in response to an indication that the pipeline does not contain any pending snoop transactions, preventing, all new transactions from entering the pipeline; and, in response to an indication that the pipeline does not contain any pending transactions, performing the global operation on the L2 cache.

公开(公告)号：US11714754B2

公开(公告)日：2023-08-01

申请号：US17460410

申请日：2021-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Naveen Bhoria

IPC: G06F12/0811 ,  G06F9/30 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F11/30 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0817 ,  G06F12/0831 ,  G06F12/084 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/16 ,  G06F12/0897

CPC classification number: G06F12/0811 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/3867 ,  G06F9/467 ,  G06F9/544 ,  G06F9/546 ,  G06F11/3037 ,  G06F12/084 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/1668 ,  G06F2212/1021 ,  G06F2212/608

Abstract: An apparatus including a CPU core and a L1 cache subsystem coupled to the CPU core. The L1 cache subsystem includes a L1 main cache, a L1 victim cache, and a L1 controller. The apparatus includes a L2 cache subsystem coupled to the L1 cache subsystem. The L2 cache subsystem includes a L2 main cache, a shadow L1 main cache, a shadow L1 victim cache, and a L2 controller. The L2 controller receives an indication from the L1 controller that a cache line A is being relocated from the L1 main cache to the L1 victim cache; in response to the indication, update the shadow L1 main cache to reflect that the cache line A is no longer located in the L1 main cache; and in response to the indication, update the shadow L1 victim cache to reflect that the cache line A is located in the L1 victim cache.

公开(公告)号：US20230185719A1

公开(公告)日：2023-06-15

申请号：US18167921

申请日：2023-02-13

Applicant: Texas Instruments Incorporated

Inventor： Abhijeet Ashok Chachad ,  Timothy David Anderson ,  Kai Chirca ,  David Matthew Thompson

IPC: G06F12/0842 ,  G06F12/0811 ,  G06F1/14 ,  G06F12/0888 ,  G06F9/54

CPC classification number: G06F12/0842 ,  G06F12/0811 ,  G06F1/14 ,  G06F12/0888 ,  G06F9/544 ,  G06F2212/1016

Abstract: In described examples, a processor system includes a processor core generating memory transactions, a lower level cache memory with a lower memory controller, and a higher level cache memory with a higher memory controller having a memory pipeline. The higher memory controller is connected to the lower memory controller by a bypass path that skips the memory pipeline. The higher memory controller: determines whether a memory transaction is a bypass write, which is a memory write request indicated not to result in a corresponding write being directed to the higher level cache memory; if the memory transaction is determined a bypass write, determines whether a memory transaction that prevents passing is in the memory pipeline; and if no transaction that prevents passing is determined to be in the memory pipeline, sends the memory transaction to the lower memory controller using the bypass path.

公开(公告)号：US11675700B2

公开(公告)日：2023-06-13

申请号：US17666196

申请日：2022-02-07

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Abhijeet Ashok Chachad ,  David Matthew Thompson ,  Timothy David Anderson ,  Kai Chirca

IPC: G06F12/08 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/128 ,  G06F12/0817 ,  G06F12/084 ,  G06F9/30 ,  G06F11/30 ,  G06F12/0808 ,  G06F13/16 ,  G06F9/38 ,  G06F9/46 ,  G06F9/54 ,  G06F12/0895 ,  G06F12/0831

CPC classification number: G06F12/0811 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/3867 ,  G06F9/467 ,  G06F9/544 ,  G06F9/546 ,  G06F11/3037 ,  G06F12/084 ,  G06F12/0808 ,  G06F12/0815 ,  G06F12/0828 ,  G06F12/0831 ,  G06F12/0895 ,  G06F12/128 ,  G06F13/1668 ,  G06F2212/1021 ,  G06F2212/608

Abstract: A method includes receiving, by a level two (L2) controller, a first request for a cache line in a shared cache coherence state; mapping, by the L2 controller, the first request to a second request for a cache line in an exclusive cache coherence state; and responding, by the L2 controller, to the second request.