公开(公告)号：US12007462B2

公开(公告)日：2024-06-11

申请号：US17351654

申请日：2021-06-18

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik Subburaj ,  Karthik Ramasubramanian ,  Shailesh Joshi ,  Kameswaran Vengattaramane ,  Indu Prathapan

IPC: G01S13/04 ,  G01S7/35 ,  G06F16/22 ,  G06F16/901 ,  G06F17/14

CPC classification number: G01S13/04 ,  G01S7/35 ,  G06F16/2264 ,  G06F16/9017 ,  G06F17/142

Abstract: A system includes a memory configured to store a two-dimensional data structure that includes radar data arranged such that radar data of a first transmitter is separated from radar data of a second transmitter by a Doppler offset in the two-dimensional data structure. The system also includes a data fetch mechanism that includes a lookup table (LUT) applied on either of two dimensions. The lookup table is configured to store a data fetch location in the two-dimensional data structure, where the data fetch location indicates a location from which to fetch a subset of the radar data from the two-dimensional data structure and the data fetch mechanism is configured to fetch the subset of the radar data from the two-dimensional data structure based on the LUT. The system includes a processor configured to perform a fast Fourier transform (FFT) on the fetched subset of the radar data.

公开(公告)号：US20240183939A1

公开(公告)日：2024-06-06

申请号：US18420133

申请日：2024-01-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sujaata Ramalingam ,  Karthik Subburaj ,  Pankaj Gupta ,  Anil Varghese Mani ,  Karthik Ramasubramanian ,  Indu Prathapan

IPC: G01S7/292 ,  G01S7/40 ,  G01S13/524

CPC classification number: G01S7/2922 ,  G01S7/4004 ,  G01S13/5246

Abstract: In a system a register stores data samples and includes a cell under test (CUT) in which a test data sample is stored, a first window of multiple cells on one side of the CUT, and a second window of multiple cells on the other side of the CUT. A rank determining circuit receives an incoming data sample entering the register and data sample(s) currently in cell(s) in the first window of multiple cells. A sorted index array stores ranks of data samples that are stored in the register. Comparing and selection circuitry selects a Kth smallest index from the sorted index array and a corresponding data sample from the register. A target comparator receives the test data sample and the data sample corresponding to the Kth smallest index of the sorted index array, and outputs a target detection signal.

公开(公告)号：US11988769B2

公开(公告)日：2024-05-21

申请号：US17856109

申请日：2022-07-01

Applicant: Texas Instruments Incorporated

Inventor： Sandeep Rao ,  Karthik Subburaj ,  Dan Wang ,  Adeel Ahmad

IPC: G01S13/34 ,  G01S7/35 ,  G01S13/42 ,  G01S13/92

CPC classification number: G01S7/354 ,  G01S13/343 ,  G01S13/42 ,  G01S13/92 ,  G01S7/356

Abstract: In accordance with described examples, a method determines if a velocity of an object detected by a radar is greater than a maximum velocity by receiving on a plurality of receivers at least one frame of chirps transmitted by at least two transmitters and reflected off of the object. A velocity induced phase shift (φd) in a virtual array vector S of signals received by each receiver corresponding to a sequence of chirps (frame) transmitted by each transmitter is estimated. Phases of each element of virtual array vector S are corrected using φd to generate a corrected virtual array vector Sc. A first Fourier transform is performed on the corrected virtual array vector Sc to generate a corrected virtual array spectrum to detect a signature that indicates that the object has an absolute velocity greater than a maximum velocity.

公开(公告)号：US11815621B2

公开(公告)日：2023-11-14

申请号：US17368319

申请日：2021-07-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sriram Murali ,  Karthik Subburaj ,  Karthik Ramasubramanian

IPC: G01S7/35 ,  G01S7/40 ,  G01S13/931

CPC classification number: G01S7/352 ,  G01S7/4021 ,  G01S13/931 ,  G01S7/358 ,  G01S7/406

Abstract: A radar system is provided that includes a receive channel configured to receive a reflected signal and to generate a first digital intermediate frequency (IF) signal based on the reflected signal, a reference receive channel configured to receive a reflected signal and to generate a second digital IF signal based on the reflected signal, and digital mismatch compensation circuitry coupled to receive the first digital IF signal and the second digital IF signal, the digital mismatch compensation circuitry configured to process the first digital IF signal and the second digital IF signal to compensate for mismatches between the receive channel and the reference receive channel.

公开(公告)号：US11650285B2

公开(公告)日：2023-05-16

申请号：US16036011

申请日：2018-07-16

Applicant: Texas Instruments Incorporated

Inventor： Sachin Bharadwaj ,  Karthik Subburaj

IPC: G01S13/34 ,  G01S7/35 ,  G01S13/58 ,  G01S7/40 ,  H03L7/06 ,  H03L7/08 ,  H03L7/12

CPC classification number: G01S7/35 ,  G01S7/4008 ,  G01S13/343 ,  G01S13/583 ,  H03L7/06 ,  H03L7/0805 ,  H03L7/12 ,  G01S13/584

Abstract: The disclosure provides a radar apparatus. The radar apparatus includes a transmit unit that generates a first signal in response to a reference clock and a feedback clock. The first signal is scattered by one or more obstacles to generate a second signal. A receive unit receives the second signal and generates N samples corresponding to the second signal. N is an integer. A conditioning circuit is coupled to the transmit unit and the receive unit. The conditioning circuit receives the N samples corresponding to the second signal, and generates N new samples using an error between the feedback clock and the reference clock.

公开(公告)号：US20230094118A1

公开(公告)日：2023-03-30

申请号：US17486435

申请日：2021-09-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Karthik Subburaj ,  Sandeep Rao

IPC: G01S7/35 ,  G01S13/931 ,  G01S13/58

Abstract: An apparatus comprises processor cores and computer-readable mediums storing machine instructions for the processor cores. When executing the machine instructions, the processor cores obtain received signals for transmitted chirps from a radar sensor circuit. Each transmitted chirp comprises an A chirp segment, a time gap, and a B chirp segment, respectively. The processor cores sample the received signals to obtain sampled data matrices M1(A) for the A chirp segments and M1(B) for the B chirp segments. The processor cores perform a first Fourier transform (FT) on each column of M1(A) and M1(B) to obtain velocity matrices M2(A) and M2(B), respectively. The processor cores apply a phase compensation factor to M2(B) to obtain a phase corrected velocity matrix M2(B′), and concatenate M2(A) and M2(B′) to obtain an aggregate velocity matrix M2(A&B′). The processor cores perform a second FT on each row of M2(A&B′) to obtain a range and velocity matrix M3(A&B′).

公开(公告)号：US11579284B2

公开(公告)日：2023-02-14

申请号：US17068976

申请日：2020-10-13

Applicant: Texas Instruments Incorporated

Inventor： Sachin Bharadwaj ,  Karthik Subburaj ,  Sriram Murali

IPC: G01S13/44 ,  G01S7/40 ,  G01S13/30 ,  G01S13/90 ,  G06V10/20 ,  G06V10/42 ,  G01S7/35

Abstract: A radar system is provided that includes transmission signal generation circuitry, a transmit channel coupled to the transmission generation circuitry to receive a continuous wave test signal, the transmit channel configurable to output a test signal based on the continuous wave signal in which a phase angle of the test signal is changed in discrete steps within a phase angle range, a receive channel coupled to the transmit channel via a feedback loop to receive the test signal, the receive channel including an in-phase (I) channel and a quadrature (Q) channel, a statistics collection module configured to collect energy measurements of the test signal output by the I channel and the test signal output by the Q channel at each phase angle, and a processor configured to estimate phase and gain imbalance of the I channel and the Q channel based on the collected energy measurements.

公开(公告)号：US11579282B2

公开(公告)日：2023-02-14

申请号：US17843069

申请日：2022-06-17

Applicant: Texas Instruments Incorporated

Inventor： Sandeep Rao ,  Karthik Subburaj ,  Sriram Murali ,  Karthik Ramasubramanian

IPC: G01S13/28 ,  G06F17/14 ,  G01S7/41 ,  G01S13/536 ,  G01S13/34 ,  G01S7/35 ,  G01S13/931 ,  G06F17/13 ,  H04N5/232

Abstract: A radar system is provided that includes a radar transceiver integrated circuit (IC) configurable to transmit a first frame of chirps, and another radar transceiver IC configurable to transmit a second frame of chirps at a time delay ΔT, wherein ΔT=Tc/K, K≥2 and Tc is an elapsed time from a start of one chirp in the first frame and the second frame and a start of a next chirp in the first frame and the second frame, wherein the radar system is configured to determine a velocity of an object in a field of view of the radar system based on first digital intermediate frequency signals generated responsive to receiving reflected chirps of the first frame and second digital IF signals generated responsive to receiving reflected chirps of the time delayed second frame, wherein the maximum measurable velocity is increased by a factor of K.

公开(公告)号：US11513190B2

公开(公告)日：2022-11-29

申请号：US16428576

申请日：2019-05-31

Applicant: Texas Instruments Incorporated

Inventor： Karthik Subburaj ,  Zahir Ibrahim Parkar ,  Krishnanshu Dandu ,  Vashishth Dudhia

IPC: G01S7/40 ,  G01S13/34 ,  G01S7/35

Abstract: Methods, apparatus, systems and articles of manufacture are disclosed to test RADAR integrated circuits. A radar circuit comprising a local oscillator (LO), a transmitter coupled to the LO and configured to be coupled to a transmission network, a receiver configured to be coupled to the transmission network, and a controller coupled to the LO, the transmitter, and the receiver, the controller to cause the LO to generate a frequency modulated continuous waveform (FMCW), cause the transmitter to modulate the FMCW as a modulated FMCW, cause the transmitter to transmit the modulated FMCW via the transmission network and the receiver to obtain a received FMCW from the transmission network, and in response to obtaining the received FMCW from the receiver, generate a performance characteristic of the radar circuit based on the received FMCW.

公开(公告)号：US20220326368A1

公开(公告)日：2022-10-13

申请号：US17843069

申请日：2022-06-17

Applicant: Texas Instruments Incorporated

Inventor： Sandeep Rao ,  Karthik Subburaj ,  Sriram Murali ,  Karthik Ramasubramanian

IPC: G01S13/28 ,  G06F17/14 ,  G01S7/41 ,  G01S13/536 ,  G01S13/931 ,  G01S13/34 ,  G01S7/35

Abstract: A radar system is provided that includes a radar transceiver integrated circuit (IC) configurable to transmit a first frame of chirps, and another radar transceiver IC configurable to transmit a second frame of chirps at a time delay ΔT, wherein ΔT=Tc/K, K≥2 and Tc is an elapsed time from a start of one chirp in the first frame and the second frame and a start of a next chirp in the first frame and the second frame, wherein the radar system is configured to determine a velocity of an object in a field of view of the radar system based on first digital intermediate frequency signals generated responsive to receiving reflected chirps of the first frame and second digital IF signals generated responsive to receiving reflected chirps of the time delayed second frame, wherein the maximum measurable velocity is increased by a factor of K.