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81.发明授权公开(公告)号：US09121820B2
公开(公告)日：2015-09-01
申请号：US13974095
申请日：2013-08-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Shao Liu , Fei-Lung Lai , Chun-Wen Cheng
IPC: H01L29/66 , G01N27/414 , H01L29/775
CPC classification number: G01N27/4145 , H01L29/66439 , H01L29/775
Abstract: The present disclosure relates to a top-down method of forming a nanowire structure extending between source and drain regions of a nanowire transistor device, and an associated apparatus. In some embodiments, the method provides a substrate having a device layer disposed over a first dielectric layer. The device layer has a source region and a drain region separated by a device material. The first dielectric layer has an embedded gate structure abutting the device layer. One or more masking layers are selectively formed over the device layer to define a nanowire structure. The device layer is then selectively etched according to the one or more masking layers to form a nanowire structure at a position between the source region and the drain region. By forming the nanowire structure through a masking and etch process, the nanowire structure is automatically connected to the source and drain regions.
Abstract translation: 本发明涉及形成在纳米线晶体管器件的源极和漏极区域之间延伸的纳米线结构的自顶向下的方法，以及相关联的器件。 在一些实施例中，该方法提供了具有设置在第一介电层上的器件层的衬底。 器件层具有由器件材料分离的源极区域和漏极区域。 第一电介质层具有邻接器件层的嵌入式栅极结构。 选择性地在器件层上形成一个或多个掩模层以限定纳米线结构。 然后根据一个或多个掩模层选择性地蚀刻器件层，以在源极区域和漏极区域之间的位置处形成纳米线结构。 通过掩模和蚀刻工艺形成纳米线结构，纳米线结构自动连接到源区和漏区。
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82.发明申请公开(公告)号：US20150053925A1
公开(公告)日：2015-02-26
申请号：US13974095
申请日：2013-08-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yi-Shao Liu , Fei-Lung Lai , Chun-Wen Cheng
IPC: G01N27/414 , H01L29/66
CPC classification number: G01N27/4145 , H01L29/66439 , H01L29/775
Abstract: The present disclosure relates to a top-down method of forming a nanowire structure extending between source and drain regions of a nanowire transistor device, and an associated apparatus. In some embodiments, the method provides a substrate having a device layer disposed over a first dielectric layer. The device layer has a source region and a drain region separated by a device material. The first dielectric layer has an embedded gate structure abutting the device layer. One or more masking layers are selectively formed over the device layer to define a nanowire structure. The device layer is then selectively etched according to the one or more masking layers to form a nanowire structure at a position between the source region and the drain region. By forming the nanowire structure through a masking and etch process, the nanowire structure is automatically connected to the source and drain regions.
Abstract translation: 本发明涉及形成在纳米线晶体管器件的源极和漏极区域之间延伸的纳米线结构的自顶向下的方法，以及相关联的器件。 在一些实施例中，该方法提供了具有设置在第一介电层上的器件层的衬底。 器件层具有由器件材料分离的源极区域和漏极区域。 第一电介质层具有邻接器件层的嵌入式栅极结构。 选择性地在器件层上形成一个或多个掩模层以限定纳米线结构。 然后根据一个或多个掩模层选择性地蚀刻器件层，以在源极区域和漏极区域之间的位置处形成纳米线结构。 通过掩模和蚀刻工艺形成纳米线结构，纳米线结构自动连接到源区和漏区。
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公开(公告)号：US11987494B2
公开(公告)日：2024-05-21
申请号：US17194492
申请日：2021-03-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tsung-Lin Hsieh , Wei-Jhih Mao , Shang-Ying Tsai , Kuei-Sung Chang , Chun-Wen Cheng
CPC classification number: B81B7/0058 , B81C1/00333 , B81B2203/0307
Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical systems (MEMS) package comprising a wire-bond damper. A housing structure overlies a support substrate, and a MEMS structure is between the support substrate and the housing structure. The MEMS structure comprises an anchor, a spring, and a movable mass. The spring extends from the anchor to the movable mass to suspend and allow movement of the movable mass in a cavity between the support substrate and the housing structure. The wire-bond damper is on the movable mass or structure surrounding the movable mass. For example, the wire-bond damper may be on a top surface of the movable mass. As another example, the wire-bond damper may be on the support substrate, laterally between the anchor and the movable mass. Further, the wire-bond damper comprises a wire formed by wire bonding and configured to dampen shock to the movable mass.
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公开(公告)号：US11667517B2
公开(公告)日：2023-06-06
申请号：US16908243
申请日：2020-06-22
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Chia Liu , Chia-Hua Chu , Chun-Wen Cheng
CPC classification number: B81B7/0006 , B81B7/0051 , B81C1/00246 , B81B2201/0257 , B81B2201/0264 , B81B2201/0271 , B81C2201/0132 , B81C2201/0133 , B81C2201/0176 , B81C2201/0181 , B81C2201/112 , B81C2203/0714 , B81C2203/0735
Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.
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公开(公告)号：US20220162058A1
公开(公告)日：2022-05-26
申请号：US17194492
申请日：2021-03-08
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Tsung-Lin Hsieh , Wei-Jhih Mao , Shang-Ying Tsai , Kuei-Sung Chang , Chun-Wen Cheng
Abstract: Various embodiments of the present disclosure are directed towards a microelectromechanical systems (MEMS) package comprising a wire-bond damper. A housing structure overlies a support substrate, and a MEMS structure is between the support substrate and the housing structure. The MEMS structure comprises an anchor, a spring, and a movable mass. The spring extends from the anchor to the movable mass to suspend and allow movement of the movable mass in a cavity between the support substrate and the housing structure. The wire-bond damper is on the movable mass or structure surrounding the movable mass. For example, the wire-bond damper may be on a top surface of the movable mass. As another example, the wire-bond damper may be on the support substrate, laterally between the anchor and the movable mass. Further, the wire-bond damper comprises a wire formed by wire bonding and configured to dampen shock to the movable mass.
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Patent Agency Ranking
公开(公告)号：US11312623B2
公开(公告)日：2022-04-26
申请号：US16944399
申请日：2020-07-31
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Yu-Chia Liu , Chia-Hua Chu , Chun-Wen Cheng , Jung-Huei Peng
Abstract: The present disclosure relates to a method of forming an integrated chip structure. The method includes forming a plurality of interconnect layers within a dielectric structure over a substrate. A dielectric layer arranged along a top of the dielectric structure is patterned to define a via hole exposing an uppermost one of the plurality of interconnect layers. An extension via is formed within the via hole and one or more conductive materials are formed over the dielectric layer and the extension via. The one or more conductive materials are patterned to define a sensing electrode over and electrically coupled to the extension via. A microelectromechanical systems (MEMS) substrate is bonded to the substrate. The MEMs substrate is vertically separated from the sensing electrode.
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公开(公告)号：US11235969B2
公开(公告)日：2022-02-01
申请号：US16420514
申请日：2019-05-23
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Wen Cheng , Chia-Hua Chu , Wen Cheng Kuo , Wei-Jhih Mao
Abstract: The integrated CMOS-MEMS device includes a CMOS structure, a cap structure, and a MEMS structure. The CMOS structure, fabricated on a first substrate, includes at least one conducting layer. The cap structure, including vias passing through the cap structure, has an isolation layer deposited on its first side and has a conductive routing layer deposited on its second side. The MEMS structure is deposited between the first substrate and the cap structure. The integrated CMOS-MEMS device also includes a conductive connector that passes through one of the vias and through an opening in the isolation layer on the cap structure. The conductive connector conductively connects a conductive path in the conductive routing layer on the cap structure with the at least one conducting layer of the CMOS structure.
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公开(公告)号：US11186481B2
公开(公告)日：2021-11-30
申请号：US16179644
申请日：2018-11-02
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor： Chen Hsiung Yang , Chun-Wen Cheng , Jiou-Kang Lee
Abstract: A sensor device includes a microelectromechanical system (MEMS) force sensor, and a capacitive acceleration sensor. In the method of manufacturing the sensor device, a sensor portion of the MEMS force sensor is prepared over a front surface of a first substrate. The sensor portion includes a piezo-resistive element and a front electrode. A bottom electrode and a first electrode are formed on a back surface of the first substrate. A second substrate having an electrode pad and a second electrode to the bottom of the first substrate are attached such that the bottom electrode is connected to the electrode pad and the first electrode faces the second electrode with a space therebetween.
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公开(公告)号：US11174158B2
公开(公告)日：2021-11-16
申请号：US16525938
申请日：2019-07-30
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Wen Cheng , Fei-Lung Lai , Kuei-Sung Chang , Shang-Ying Tsai
Abstract: In some embodiments, a sensor is provided. The sensor includes a microelectromechanical systems (MEMS) substrate disposed over an integrated chip (IC), where the IC defines a lower portion of a first cavity and a lower portion of a second cavity, and where the first cavity has a first operating pressure different than an operating pressure of the second cavity. A cap substrate is disposed over the MEMS substrate, where a first pair of sidewalls of the cap substrate partially define an upper portion of the first cavity, and a second pair of sidewalls of the cap substrate partially define an upper portion of the second cavity. A sensor area comprising a movable portion of the MEMS substrate and a dummy area comprising a fixed portion of the MEMS substrate are both disposed in the first cavity. A pressure enhancement structure is disposed in the dummy area.
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公开(公告)号：US11078074B2
公开(公告)日：2021-08-03
申请号：US16705591
申请日：2019-12-06
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor： Chun-Wen Cheng , Chia-Hua Chu
IPC: B81C1/00
Abstract: Processes for integrating complementary metal-oxide-semiconductor (CMOS) devices with microelectromechanical systems (MEMS) devices are provided. In some embodiments, the MEMS devices are formed on a sacrificial substrate or wafer, the sacrificial substrate or wafer is bonded to a CMOS die or wafer, and the sacrificial substrate or wafer is removed. In other embodiments, the MEMS devices are formed over a sacrificial region of a CMOS die or wafer and the sacrificial region is subsequently removed. Integrated circuit (ICs) resulting from the processes are also provided.
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