Semiconductor structure for MEMS Device

    公开(公告)号:US10160639B2

    公开(公告)日:2018-12-25

    申请号:US15193410

    申请日:2016-06-27

    Abstract: The present disclosure relates to a semiconductor structure for a MEMS device. In some embodiments, the structure includes an interlayer dielectric (ILD) region positioned over a substrate. Further the structure includes an inter-metal dielectric region. The IMD region includes a passivation layer overlying a stacked structure. The stacked structure includes dielectric layers and etch stop layers that are stacked in an alternating fashion. Metal wire layers are disposed within the stacked structure of the IMD region. The structure also includes a sensing electrode electrically connected to the IMD region with an electrode extension via. The structure includes a MEMS substrate comprising a MEMS device having a soft mechanical structure positioned adjacent to the sensing electrode.

    Multi-pressure MEMS package
    4.
    发明授权

    公开(公告)号:US09695039B1

    公开(公告)日:2017-07-04

    申请号:US15143762

    申请日:2016-05-02

    CPC classification number: B81B3/0051 B81B7/02 B81C2203/0118

    Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) package having two MEMS devices with different pressures, and an associated method of formation. In some embodiments, the (MEMS) package includes a device substrate and a cap substrate bonded together. The device substrate includes a first trench and a second trench. A first MEMS device is disposed over the first trench and a second MEMS device is disposed over the second trench. A first stopper is raised from a first trench bottom surface of the first trench but below a top surface of the device substrate and a second stopper is raised from a second trench bottom surface of the second trench but below the top surface of the device substrate. A first depth of the first trench is greater than a second depth of the second trench.

    Semiconductor structure for MEMS device

    公开(公告)号:US10752497B2

    公开(公告)日:2020-08-25

    申请号:US16211681

    申请日:2018-12-06

    Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure has a plurality of interconnect layers disposed within a dielectric structure over a substrate. A passivation layer is over the dielectric structure. A sensing electrode and a bonding electrode have bottom surfaces directly contacting the passivation layer. A microelectromechanical systems (MEMS) substrate is vertically separated from the sensing electrode. The bonding electrode is electrically connected to the MEMs substrate and to one or more of the plurality of interconnect layers. An electrode extension via is configured to electrically connect the sensing electrode to one or more of the plurality of interconnect layers.

    MULTI-PRESSURE MEMS PACKAGE
    6.
    发明申请

    公开(公告)号:US20170283250A1

    公开(公告)日:2017-10-05

    申请号:US15626764

    申请日:2017-06-19

    CPC classification number: B81B3/0051 B81B7/02 B81C2203/0118

    Abstract: The present disclosure relates to a microelectromechanical systems (MEMS) package having two MEMS devices with different pressures, and an associated method of formation. In some embodiments, the (MEMS) package includes a device substrate and a cap substrate bonded together. The device substrate includes a first trench and a second trench. A first MEMS device is disposed over the first trench and a second MEMS device is disposed over the second trench. A first stopper is raised from a first trench bottom surface of the first trench but below a top surface of the device substrate and a second stopper is raised from a second trench bottom surface of the second trench but below the top surface of the device substrate. A first depth of the first trench is greater than a second depth of the second trench.

    Wafer level method of sealing different pressure levels for MEMS sensors
    7.
    发明授权
    Wafer level method of sealing different pressure levels for MEMS sensors 有权
    用于MEMS传感器密封不同压力水平的晶圆级方法

    公开(公告)号:US09029961B2

    公开(公告)日:2015-05-12

    申请号:US14013155

    申请日:2013-08-29

    Abstract: The present disclosure relates to a method of forming a plurality of MEMs device having a plurality of chambers with different pressures on a substrate, and an associated apparatus. In some embodiments, the method is performed by providing a device wafer having a plurality of microelectromechanical system (MEMs) devices. A cap wafer is bonded onto the device wafer in a first ambient environment having a first pressure. The bonding forms a plurality of chambers abutting the plurality of MEMs devices, which are held at the first pressure. One or more openings are formed in one or more of the plurality of chambers. The one or more openings in the one or more of the plurality of chambers are then sealed in a different ambient environment having a different pressure, thereby causing the one or more of the plurality of chambers to be held at the different pressure.

    Abstract translation: 本公开涉及一种在基板上形成具有多个具有不同压力的室的多个MEM装置的方法,以及相关联的装置。 在一些实施例中,该方法通过提供具有多个微机电系统(MEM)装置的装置晶片来执行。 帽盖晶片在具有第一压力的第一环境环境中结合到器件晶片上。 接合形成与多个保持在第一压力下的多个MEM装置邻接的多个室。 一个或多个开口形成在多个室中的一个或多个室中。 然后将多个腔室中的一个或多个室中的一个或多个开口密封在具有不同压力的不同环境环境中,从而使多个室中的一个或多个保持在不同的压力。

    Method and structure for CMOS-MEMS thin film encapsulation

    公开(公告)号:US12134555B2

    公开(公告)日:2024-11-05

    申请号:US18315799

    申请日:2023-05-11

    Abstract: Representative methods for sealing MEMS devices include depositing insulating material over a substrate, forming conductive vias in a first set of layers of the insulating material, and forming metal structures in a second set of layers of the insulating material. The first and second sets of layers are interleaved in alternation. A dummy insulating layer is provided as an upper-most layer of the first set of layers. Portions of the first and second set of layers are etched to form void regions in the insulating material. A conductive pad is formed on and in a top surface of the insulating material. The void regions are sealed with an encapsulating structure. At least a portion of the encapsulating structure is laterally adjacent the dummy insulating layer, and above a top surface of the conductive pad. An etch is performed to remove at least a portion of the dummy insulating layer.

    METHOD FOR MANUFACTURING A MICROELECTROMECHANICAL SYSTEMS (MEMS) DEVICE WITH DIFFERENT ELECTRICAL POTENTIALS AND AN ETCH STOP
    10.
    发明申请
    METHOD FOR MANUFACTURING A MICROELECTROMECHANICAL SYSTEMS (MEMS) DEVICE WITH DIFFERENT ELECTRICAL POTENTIALS AND AN ETCH STOP 有权
    用于制造具有不同电位和延迟的微电子系统(MEMS)器件的方法

    公开(公告)号:US20160031703A1

    公开(公告)日:2016-02-04

    申请号:US14880375

    申请日:2015-10-12

    Abstract: A semiconductor structure for a microelectromechanical systems (MEMS) device is provided. A first substrate region includes an electrical isolation layer arranged over a top surface of the first substrate region. A second substrate region is arranged over the electrical isolation layer and includes a MEMS device structure arranged within the second substrate region. The MEMS device structure includes a fixed mass and a proof mass. A dielectric region is arranged over the electrical isolation layer around the fixed mass. A fixed mass electrode is arranged around the dielectric region, and extends through the second substrate region to the electrical isolation layer. An isolated electrode extends through the second substrate region and the electrical isolation layer to the first substrate region on an opposite side of the proof mass as the fixed mass electrode. The method of forming the semiconductor structure is also provided.

    Abstract translation: 提供了一种用于微机电系统(MEMS)装置的半导体结构。 第一衬底区域包括布置在第一衬底区域的顶表面上方的电隔离层。 第二衬底区域布置在电隔离层上方并且包括布置在第二衬底区域内的MEMS器件结构。 MEMS器件结构包括固定质量和检验质量。 电介质区域布置在固定质量块周围的电隔离层的上方。 固定质量电极布置在电介质区周围,并且延伸穿过第二衬底区域到电隔离层。 隔离电极通过第二衬底区域和电隔离层延伸到与固定质量电极相反的一侧的第一衬底区域。 还提供了形成半导体结构的方法。

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