公开(公告)号：US20200043919A1

公开(公告)日：2020-02-06

申请号：US16215676

申请日：2018-12-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Huan-Chieh Su ,  Mao-Lin Huang ,  Zhi-Chang Lin

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/8234

Abstract: Provided are FinFET devices and methods of forming the same. A FinFET device includes a substrate, a metal gate strip, gate spacers and a dielectric helmet. The substrate has fins. The metal gate strip is disposed across the fins and has a reversed T-shaped portion between two adjacent fins. The gate spacers are disposed on opposing sidewalls of the metal gate strip. A dielectric helmet is disposed over the metal gate strip.

公开(公告)号：US10516051B2

公开(公告)日：2019-12-24

申请号：US15235233

申请日：2016-08-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kuan-Ting Pan ,  Ching-Wei Tsai ,  Ying-Keung Leung ,  Chih-Hao Wang ,  Carlos H. Diaz

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51

Abstract: The present disclosure provides a fin-like field effect transistor (FinFET) device and a method of fabrication thereof. The method includes forming a fin on a substrate and forming a gate structure wrapping the fin. A pair of spacers is formed adjacent to the gate structure and the gate structure is removed. Afterwards, a pair of oxide layers is deposited adjacent to the pair of spacers. A pair of gate dielectric layers is deposited next to the pair of oxide layers. Finally, a metal gate is formed between the pair of gate dielectric layers.

公开(公告)号：US10361126B2

公开(公告)日：2019-07-23

申请号：US15987009

申请日：2018-05-23

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung ,  Carlos H. Diaz

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238

Abstract: A semiconductor layer is etched into a plurality of fin structures. A first nitridation process is performed to side surfaces of the fin structures. The first nitridation process forms a first oxynitride layer at the side surfaces of the fin structures. A liner oxide layer is formed on the first oxynitride layer. An isolation structure is formed around the fin structures after the forming of the liner oxide layer.

公开(公告)号：US20190164840A1

公开(公告)日：2019-05-30

申请号：US16246209

申请日：2019-01-11

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Kuan-Ting Pan

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions. The method also includes forming first and second source/drain regions on first and second recessed portions of the first and second fin structures, respectively and replacing the first and second polysilicon structures with first and second gate structures, respectively

公开(公告)号：US20190081153A1

公开(公告)日：2019-03-14

申请号：US16186783

申请日：2018-11-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/02 ,  H01L29/51 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/78

CPC classification number: H01L29/6653 ,  H01L21/0214 ,  H01L21/02247 ,  H01L21/02271 ,  H01L21/31116 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/513 ,  H01L29/518 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/7851

Abstract: A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a lower portion and an upper portion extending upwards from the lower portion. The bottom capping structure covers a sidewall of the lower portion of the fin. The top capping structure covers a sidewall of the upper portion of the fin.

公开(公告)号：US20190035785A1

公开(公告)日：2019-01-31

申请号：US15698030

申请日：2017-09-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66

Abstract: Various examples of a buried interconnect line are disclosed herein. In an example, a device includes a fin disposed on a substrate. The fin includes an active device. A plurality of isolation features are disposed on the substrate and below the active device. An interconnect is disposed on the substrate and between the plurality of isolation features such that the interconnect is below a topmost surface of the plurality of isolation features. The interconnect is electrically coupled to the active device. In some such examples, a gate stack of the active device is disposed over a channel region of the active device and is electrically coupled to the interconnect. In some such examples, a source/drain contact is electrically coupled to a source/drain region of the active device, and the source/drain contact is electrically coupled to the interconnect.

公开(公告)号：US10134870B2

公开(公告)日：2018-11-20

申请号：US15409617

申请日：2017-01-19

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Shi-Ning Ju ,  Chih-Hao Wang ,  Ying-Keung Leung

IPC: H01L21/82 ,  H01L29/66 ,  H01L21/02 ,  H01L29/51 ,  H01L21/311

Abstract: A semiconductor structure includes a substrate, a fin, a bottom capping structure and a top capping structure. The fin disposed on the substrate, the fin has a lower portion and an upper portion extending upwards from the lower portion. The bottom capping structure covers a sidewall of the lower portion of the fin. The top capping structure covers a sidewall of the upper portion of the fin.

公开(公告)号：US09991262B1

公开(公告)日：2018-06-05

申请号：US15623499

申请日：2017-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/04 ,  H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L21/8238

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L21/823878 ,  H01L29/045 ,  H01L29/0642 ,  H01L29/161 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device includes PMOS and NMOS FinFET devices disposed on a hybrid substrate including a first substrate and a second substrate, in which a fin of the PMOS FinFET device is formed on the first substrate having a top surface with a (100) crystal orientation, and another fin of the NMOS FinFET device is formed on the second substrate having a top surface with a (110) crystal orientation. The semiconductor device further includes a capping layer enclosing a buried bottom portion of the fin of the PMOS FinFET device, and another capping layer enclosing an effective channel portion of the fin of the PMOS FinFET device.

公开(公告)号：US09922978B2

公开(公告)日：2018-03-20

申请号：US14832086

申请日：2015-08-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD

Inventor： Kuo-Cheng Ching ,  Ching-Wei Tsai ,  Ying-Keung Leung

IPC: H01L27/092 ,  H01L29/417 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/66 ,  H01L29/45

CPC classification number: H01L27/0924 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/665 ,  H01L29/6653

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a fin structure formed over a substrate and a first gate structure formed across the fin structure. The semiconductor structure further includes a first source/drain structure formed in the fin structure adjacent to the first gate structure and a first contact formed over the first source/drain structure. In addition, the first contact includes a first extending portion extending into the first source/drain structure.

公开(公告)号：US12211921B2

公开(公告)日：2025-01-28

申请号：US17576854

申请日：2022-01-14

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Kuo-Cheng Ching ,  Kai-Chieh Yang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang

IPC: H01L21/28 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

Abstract: Aspects of the disclosure provide a method for forming a fin field effect transistor (FinFET) incorporating a fin top hardmask on top of a channel region of a fin. Because of the presence of the fin top hardmask, a gate height of the FinFET can be reduced without affecting proper operations of vertical gate channels on sidewalls of the fin. Consequently, parasitic capacitance between a gate stack and source/drain contacts of the FinFET can be reduced by lowering the gate height of the FinFET.