公开(公告)号：US11592618B2

公开(公告)日：2023-02-28

申请号：US17226542

申请日：2021-04-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsing-Kuo Hsia ,  Chen-Hua Yu ,  Kuo-Chiang Ting ,  Shang-Yun Hou

IPC: G02B6/12 ,  G02B6/13 ,  G02B6/124

Abstract: A method includes forming a first photonic package, wherein forming the first photonic package includes patterning a silicon layer to form a first waveguide, wherein the silicon layer is on an oxide layer, and wherein the oxide layer is on a substrate; forming vias extending into the substrate; forming a first redistribution structure over the first waveguide and the vias, wherein the first redistribution structure is electrically connected to the vias; connecting a first semiconductor device to the first redistribution structure; removing a first portion of the substrate to form a first recess, wherein the first recess exposes the oxide layer; and filling the first recess with a first dielectric material to form a first dielectric region.

公开(公告)号：US20230053190A1

公开(公告)日：2023-02-16

申请号：US17977301

申请日：2022-10-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Hui Lai ,  Shu-Rong Chun ,  Kuo Lung Pan ,  Tin-Hao Kuo ,  Hao-Yi Tsai ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L23/538 ,  H01L21/56 ,  H01L23/31 ,  H01L23/00 ,  H01L21/48

Abstract: In an embodiment, a device includes: a package component including: a first integrated circuit die; an encapsulant at least partially surrounding the first integrated circuit die; a redistribution structure on the encapsulant, the redistribution structure physically and electrically coupling the first integrated circuit die; a first module socket attached to the redistribution structure; an interposer attached to the redistribution structure adjacent the first module socket, the outermost extent of the interposer extending beyond the outermost extent of the redistribution structure; and an external connector attached to the interposer.

公开(公告)号：US11532540B2

公开(公告)日：2022-12-20

申请号：US16927020

申请日：2020-07-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo ,  Chen-Hua Yu

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L23/522

Abstract: A method includes forming a buffer dielectric layer over a carrier, and forming a first dielectric layer and a first redistribution line over the buffer dielectric layer. The first redistribution line is in the first dielectric layer. The method further includes performing a planarization on the first dielectric layer to level a top surface of the first dielectric layer, forming a metal post over and electrically coupling to the first redistribution line, and encapsulating the metal post in an encapsulating material. The encapsulating material contacts a top surface of the planarized top surface of the first dielectric layer.

公开(公告)号：US11527466B2

公开(公告)日：2022-12-13

申请号：US17222118

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Yun Chen Hsieh ,  Hui-Jung Tsai ,  Hung-Jui Kuo

IPC: H01L23/498 ,  H01L21/288 ,  H01L21/3213 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L21/768 ,  H01L21/78 ,  H01L21/66 ,  H01L23/31 ,  H01L23/00 ,  H01L21/285 ,  H01L23/482

Abstract: Embodiments include forming a die, the die including a pad and a passivation layer over the pad. A via is formed to the pad through the passivation layer. A solder cap is formed on the via, where a first material of the solder cap flows to the sidewall of the via. In some embodiments, the via is encapsulated in a first encapsulant, where the first encapsulant is a polymer or molding compound selected to have a low co-efficient of thermal expansion and/or low curing temperature. In some embodiments, the first material of the solder cap is removed from the sidewall of the via by an etching process and the via is encapsulated in a first encapsulant.

公开(公告)号：US11527465B2

公开(公告)日：2022-12-13

申请号：US17222088

申请日：2021-04-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Sung-Feng Yeh ,  Ming-Fa Chen ,  Hsien-Wei Chen

IPC: H01L23/498 ,  H01L25/10 ,  H01L25/00 ,  H01L21/683 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, forming stacked vias in the plurality of dielectric layers with the stacked vias forming a continuous electrical connection penetrating through the plurality of dielectric layers, forming a dielectric layer over the stacked vias and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, and bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding.

公开(公告)号：US11527454B2

公开(公告)日：2022-12-13

申请号：US17362185

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wen-Hsin Wei ,  Chi-Hsi Wu ,  Shang-Yun Hou ,  Jing-Cheng Lin ,  Hsien-Pin Hu ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC: H01L23/31 ,  H01L23/16 ,  H01L21/56 ,  H01L23/14 ,  H01L21/48 ,  H01L25/03 ,  H01L25/065 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/00

Abstract: An embodiment is a method including: attaching a first die to a first side of a first component using first electrical connectors, attaching a first side of a second die to first side of the first component using second electrical connectors, attaching a dummy die to the first side of the first component in a scribe line region of the first component, adhering a cover structure to a second side of the second die, and singulating the first component and the dummy die to form a package structure.

公开(公告)号：US11515229B2

公开(公告)日：2022-11-29

申请号：US16835322

申请日：2020-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Lai ,  Chien-Chia Chiu ,  Chen-Hua Yu ,  Der-Chyang Yeh ,  Cheng-Hsien Hsieh ,  Li-Han Hsu ,  Tsung-Shu Lin ,  Wei-Cheng Wu ,  Yu-Chen Hsu

IPC: H01L23/367 ,  H01L23/31 ,  H01L25/065 ,  H01L21/56 ,  H01L23/498 ,  H01L23/538 ,  H01L21/52 ,  H01L25/00

Abstract: A semiconductor package includes a circuit substrate, a die, a frame structure, a heat sink lid and conductive balls. The die is disposed on a front surface of the circuit substrate and electrically connected with the circuit substrate. The die includes two first dies disposed side by side and separate from each other with a gap between two facing sidewalls of the two first dies. The frame structure is disposed on the front surface of the circuit substrate and surrounding the die. The heat sink lid is disposed on the die and the frame structure. The head sink lid has a slit that penetrates through the heat sink lid in a thickness direction and exposes the gap between the two facing sidewalls of the two first dies. The conductive balls are disposed on the opposite surface of the circuit substrate and electrically connected with the die through the circuit substrate.

公开(公告)号：US20220375839A1

公开(公告)日：2022-11-24

申请号：US17815421

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ming-Fa Chen ,  Chen-Hua Yu

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/14 ,  G01R1/04 ,  H01L23/32 ,  H05K7/10 ,  H01L25/065 ,  H05K3/46 ,  H01L21/683 ,  H01L23/00

Abstract: A method includes forming a plurality of dielectric layers, forming a plurality of redistribution lines in the plurality of dielectric layers, etching the plurality of dielectric layers to form an opening, filling the opening to form a through-dielectric via penetrating through the plurality of dielectric layers, forming a dielectric layer over the through-dielectric via and the plurality of dielectric layers, forming a plurality of bond pads in the dielectric layer, bonding a device die to the dielectric layer and a first portion of the plurality of bond pads through hybrid bonding, and bonding a die stack to through-silicon vias in the device die.

公开(公告)号：US20220375814A1

公开(公告)日：2022-11-24

申请号：US17883348

申请日：2022-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Li-Chung Kuo ,  Ying-Ching Shih ,  Szu-Wei Lu

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/48 ,  H01L23/31 ,  H01L23/00

Abstract: 3D semiconductor packages and methods of forming 3D semiconductor package are described herein. The 3D semiconductor packages are formed by mounting a die stack on an interposer, dispensing a thermal interface material (TIM) layer over the die stack and placing a heat spreading element over and attached to the die stack by the TIM layer. The TIM layer provides a reliable adhesion layer and an efficient thermally conductive path between the die stack and interposer to the heat spreading element. As such, delamination of the TIM layer from the heat spreading element is prevented, efficient heat transfer from the die stack to the heat spreading element is provided, and a thermal resistance along thermal paths through the TIM layer between the interposer and heat spreading element are reduced. Thus, the TIM layer reduces overall operating temperatures and increases overall reliability of the 3D semiconductor packages.

公开(公告)号：US20220367466A1

公开(公告)日：2022-11-17

申请号：US17870296

申请日：2022-07-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Hsien-Wei Chen ,  Wen-Chih Chiou ,  Ming-Fa Chen ,  Sung-Feng Yeh

IPC: H01L27/105 ,  H01L27/146

Abstract: A semiconductor device and method of manufacture are provided wherein the semiconductor device includes a first system on chip device bonded to a first memory device, a second system on chip device bonded to the first memory device, a first encapsulant surrounding the first system on chip device and the second system on chip device, a second encapsulant surrounding the first system on chip device, the second system on chip device, and the first memory device, and a through via extending from a first side of the second encapsulant to a second side of the first encapsulant, the through via being located outside of the first encapsulant.