公开(公告)号：US06025629A

公开(公告)日：2000-02-15

申请号：US746527

申请日：1996-11-12

Applicant: Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yasuo Yamaguchi

Inventor： Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yasuo Yamaguchi

IPC: H01L21/76 ,  H01L21/336 ,  H01L21/762 ,  H01L27/12 ,  H01L29/06 ,  H01L29/786 ,  H01L29/00

CPC classification number: H01L29/66772 ,  H01L21/76224 ,  H01L21/76264 ,  H01L29/0638 ,  H01L29/78609 ,  H01L21/76281

Abstract: A sidewall oxide layer and a sidewall insulation layer are formed to cover the edge portion of an SOI layer. A channel stopper region is formed in the vicinity of the edge portion of the SOI layer. A protruded insulation layer is formed on the channel stopper region. A gate electrode extends from a region over the SOI layer to the protruded insulation layer and the sidewall insulation layer. In this way, reduction in threshold voltage Vth of a parasitic MOS transistor at the edge portion of the SOI layer can be suppressed.

Abstract translation: 形成侧壁氧化物层和侧壁绝缘层以覆盖SOI层的边缘部分。 在SOI层的边缘部附近形成沟道阻挡区域。 在沟道阻挡区域上形成突出的绝缘层。 栅电极从SOI层上的区域延伸到突出的绝缘层和侧壁绝缘层。 以这种方式，可以抑制在SOI层的边缘部分处的寄生MOS晶体管的阈值电压Vth的降低。

公开(公告)号：US5933745A

公开(公告)日：1999-08-03

申请号：US947339

申请日：1997-10-08

Applicant: Toshiaki Iwamatsu ,  Takashi Ipposhi

Inventor： Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L21/76297 ,  H01L21/7624 ,  H01L21/76264 ,  H01L21/76281

Abstract: A semiconductor integrated circuit is formed by MESA isolation of a thin film silicon layer, in which transistor characteristics are free from influence depending on pattern density of transistor forming regions. The thin film silicon layer on an insulating substrate is isolated by MESA isolation, and element forming regions are formed. In the middle part of a large distance between adjacent element forming regions, a LOCOS oxide film is thickly formed, and an oxide film is filled-in or buried between the LOCOS oxide film and the element forming regions contiguously at the same surface level so that there is no step-like level difference therebetween.

Abstract translation: 通过薄膜硅层的MESA隔离来形成半导体集成电路，其中晶体管特性根据晶体管形成区域的图案密度而不受影响。 通过MESA隔离隔离绝缘基板上的薄膜硅层，形成元件形成区域。 在相邻的元件形成区域之间的大距离的中间部分，厚厚地形成LOCOS氧化物膜，并且在相同的表面水平下将氧化膜填充或掩埋在LOCOS氧化物膜和元件形成区域之间，使得 其间没有阶梯状的水平差。

公开(公告)号：US5357365A

公开(公告)日：1994-10-18

申请号：US62631

申请日：1993-05-18

Applicant: Takashi Ipposhi ,  Tadashi Nishimura

Inventor： Takashi Ipposhi ,  Tadashi Nishimura

IPC: B01J19/12 ,  B23K26/06 ,  B23K26/08 ,  C30B1/08 ,  H01L21/268 ,  H01S3/101 ,  G02B26/08 ,  H01L21/477

CPC classification number: B23K26/08 ,  B23K26/06 ,  B23K26/064 ,  B23K26/0648 ,  B23K26/0665 ,  B23K26/082 ,  Y10S117/904 ,  Y10S359/90

Abstract: A laser beam irradiating apparatus is capable of laser annealing with high precision and uniform over the entire surface of a sample. Luminous flux of the laser beam output from a laser source is expanded by a beam expander. The power of the laser beam which has passed through the beam expander is adjusted by a half-wave plate of synthetic quarts and a polarizing prism of synthetic quarts. The laser beam emitted from polarizing prism is guided to a prescribed position by mirrors, and swung in the direction of the X-axis by an X-axis rotation mirror. The laser beam reflected from X-axis rotation mirror has its diameter reduced by a f-.theta. lens to have a prescribed beam spot diameter on the surface of a silicon wafer, and laser beam scanning is carried out at a constant speed. Since half-wave plate and the polarizing prism are formed of synthetic quarts, thermal deformation of optical components caused by continuous irradiation of laser beam can be suppressed, beam profile of the laser beam can be stabilized, therefore highly uniform and highly precise laser annealing becomes possible.

Abstract translation: 激光束照射装置能够在样品的整个表面上以高精度和均匀的激光退火。 从激光源输出的激光束的光通量由光束扩展器扩展。 已经通过扩束器的激光束的功率由合成夸脱的半波片和合成夸脱的偏振棱镜调节。 从偏振棱镜发射的激光束被反射镜引导到规定位置，并通过X轴旋转镜在X轴的方向上摆动。 从X轴旋转镜反射的激光束的直径通过f-θ透镜减小，以在硅晶片的表面上具有规定的光束点直径，并且以恒定的速度执行激光束扫描。 由于半波片和偏光棱镜由合成石英形成，可以抑制由激光束的连续照射引起的光学部件的热变形，激光束的光束轮廓可以稳定，因此高度均匀且高精度的激光退火成为 可能。

公开(公告)号：US07741679B2

公开(公告)日：2010-06-22

申请号：US11866693

申请日：2007-10-03

Applicant: Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

Inventor： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC: H01L23/62

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.

Abstract translation: 在其之间形成的具有阱区的部分氧化膜彼此隔离SOI层中的晶体管形成区域。 在部分氧化膜的下部形成有p型阱区，其将NMOS晶体管彼此隔离，并且在部分氧化膜的下部形成n型阱区，其将PMOS晶体管彼此隔离。 p型阱区域和n型阱区域在部分氧化膜的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域接触。 形成在层间绝缘膜上的互连层通过设置在层间绝缘膜中的体接触电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US20090194877A1

公开(公告)日：2009-08-06

申请号：US12399062

申请日：2009-03-06

Applicant: Yukio Maki ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

Inventor： Yukio Maki ,  Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC: H01L23/532 ,  H01L21/84 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L21/743 ,  H01L23/585 ,  H01L27/1203 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A plurality of conductive layers and a plurality of wiring layers connecting a supporting substrate having SOI structure and uppermost wire are formed along a peripheral part of a semiconductor chip together with the uppermost wire, to thereby surround a transistor forming region in which a transistor is to be formed.

Abstract translation: 沿着半导体芯片的周边部分与最上面的导线一起形成多个导电层和连接具有SOI结构的支撑衬底和最上面的线的多个布线层，从而围绕晶体管形成区域 形成。

公开(公告)号：US20090162980A1

公开(公告)日：2009-06-25

申请号：US12354540

申请日：2009-01-15

Applicant: Takashi Ipposhi

Inventor： Takashi Ipposhi

IPC: H01L21/336

CPC classification number: H01L29/0847 ,  H01L21/76281 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6656 ,  H01L29/7833

Abstract: An oxide film is formed on an SOI layer, an isolation oxide film and a gate electrode. A nitride film is formed on the oxide film. Next, anisotropic etching is performed only on the nitride film to form sidewalls on opposite side surfaces of the gate electrode. Thus, the oxide film is not etched. Next, an N-type impurity is implanted through the oxide film to form source/drain regions in an upper portion of the SOI layer. In this step, adjusting the implantation energy so that the impurity reaches the buried oxide film provides the source/drain regions in contact with the buried oxide film.

Abstract translation: 在SOI层，隔离氧化膜和栅电极上形成氧化膜。 在氧化膜上形成氮化膜。 接下来，仅在氮化膜上进行各向异性蚀刻，以在栅电极的相对侧表面上形成侧壁。 因此，氧化膜不被蚀刻。 接下来，通过氧化膜注入N型杂质，以在SOI层的上部形成源/漏区。 在该步骤中，调整注入能量使得杂质到达掩埋氧化膜，使源/漏区与掩埋氧化膜接触。

公开(公告)号：US07541644B2

公开(公告)日：2009-06-02

申请号：US10793841

申请日：2004-03-08

Applicant: Yuuichi Hirano ,  Shigenobu Maeda ,  Takuji Matsumoto ,  Takashi Ipposhi ,  Shigeto Maegawa

Inventor： Yuuichi Hirano ,  Shigenobu Maeda ,  Takuji Matsumoto ,  Takashi Ipposhi ,  Shigeto Maegawa

IPC: H01L29/72

CPC classification number: H01L23/481 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/78639 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The semiconductor device has a silicon layer (SOI layer) (12) formed through a silicon oxide film (11) on a support substrate (10). A transistor (T1) is formed in the SOI layer (12). The wiring (17a) is connected with a source of the transistor (T1) through a contact plug (15a). A back metal (18) is formed on an under surface (back surface) of the support substrate (10) and said back metal (18) is connected with the wiring (17a) through a heat radiating plug (16). The contact plug (15a), the heat radiating plug (16) the wiring (17a) and the back metal (18) is made of a metal such as aluminum, tungsten and so on which has a higher thermal conductivity than that of the silicon oxide film (11) and the support substrate (10).

Abstract translation: 半导体器件具有通过支撑衬底（10）上的氧化硅膜（11）形成的硅层（SOI层）（12）。 在SOI层（12）中形成晶体管（T1）。 布线（17a）通过接触插塞（15a）与晶体管（T1）的源极连接。 背衬金属（18）形成在支撑基板（10）的下表面（背面）上，背面金属（18）通过散热塞（16）与布线17a连接。 接触插头（15a），散热塞（16），布线（17a）和背金属（18）由诸如铝，钨等的金属制成，其具有比硅的热导率更高的导热性 氧化膜（11）和支撑基板（10）。

公开(公告)号：US07504291B2

公开(公告)日：2009-03-17

申请号：US11929626

申请日：2007-10-30

Applicant: Shigenobu Maeda ,  Takuji Matsumoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

Inventor： Shigenobu Maeda ,  Takuji Matsumoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC: H01L21/84

CPC classification number: H01L29/66772 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/7841 ,  H01L29/78615 ,  H01L29/78654 ,  Y10S438/981

Abstract: It is an object to provide an SOI device capable of carrying out body fixation and implementing a quick and stable operation. A gate insulating film (11) having a thickness of 1 to 5 nm is provided between a portion other than a gate contact pad (GP) of a gate electrode (12) and an SOI layer (3), and a gate insulating film (110) having a thickness of 5 to 15 nm is provided between the gate contact pad (GP) and the SOI layer (3). The gate insulating film (11) and the gate insulating film (110) are provided continuously.

Abstract translation: 本发明的目的是提供一种能够进行身体固定并实现快速稳定的操作的SOI装置。 在栅极（12）的栅极接触焊盘（GP）与SOI层（3）之间的部分之间设置厚度为1〜5nm的栅极绝缘膜（11）和栅极绝缘膜（ 在栅极接触焊盘（GP）和SOI层（3）之间设置有厚度为5〜15nm的光栅（110）。 连续设置栅极绝缘膜（11）和栅极绝缘膜（110）。

公开(公告)号：US20080315313A1

公开(公告)日：2008-12-25

申请号：US11866693

申请日：2007-10-03

Applicant: Yasuo YAMAGUCHI ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

Inventor： Yasuo YAMAGUCHI ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: A partial oxide film with well regions formed therebeneath isolates transistor formation regions in an SOI layer from each other. A p-type well region is formed beneath part of the partial oxide film which isolates NMOS transistors from each other, and an n-type well region is formed beneath part of the partial oxide film which isolates PMOS transistors from each other. The p-type well region and the n-type well region are formed in side-by-side relation beneath part of the partial oxide film which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region adjacent thereto. An interconnect layer formed on an interlayer insulation film is electrically connected to the body region through a body contact provided in the interlayer insulation film. A semiconductor device having an SOI structure reduces a floating-substrate effect.

Abstract translation: 在其之间形成的具有阱区的部分氧化膜彼此隔离SOI层中的晶体管形成区域。 在部分氧化膜的下部形成有p型阱区，其将NMOS晶体管彼此隔离，并且在部分氧化膜的下部形成n型阱区，其将PMOS晶体管彼此隔离。 p型阱区域和n型阱区域在部分氧化膜的一部分下方并排地形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域接触。 形成在层间绝缘膜上的互连层通过设置在层间绝缘膜中的体接触电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US20080179676A1

公开(公告)日：2008-07-31

申请号：US11971434

申请日：2008-01-09

Applicant: Yuichi HIRANO ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yukio Maki ,  Mikio Tsujiuchi

Inventor： Yuichi HIRANO ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Yukio Maki ,  Mikio Tsujiuchi

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1203

Abstract: While reducing the formation area of a SRAM cell, the variation in electrical characteristics of respective transistors is suppressed. In a SRAM cell formed in a SOI board, the electrical coupling between the drain region of a driver transistor (which is also a source/drain region of an access transistor), and the drain region of a load transistor, and the electrical coupling between the drain region of another driver transistor (which is also a source/drain region of another access transistor) and the drain region of another load transistor are established by wiring structures formed by using a SOI layer under an isolation oxide film which is partial trench isolation, respectively.

Abstract translation: 在减小SRAM单元的形成面积的同时，抑制了各个晶体管的电特性的变化。 在SOI板中形成的SRAM单元中，驱动晶体管（其也是存取晶体管的源极/漏极区域）的漏极区域与负载晶体管的漏极区域之间的电耦合以及电耦合 另一个驱动晶体管的漏极区（也是另一个存取晶体管的源极/漏极区）和另一个负载晶体管的漏极区通过在隔离氧化膜下使用SOI层而形成的布线结构来建立，该SOI层是部分沟槽隔离 ， 分别。