公开(公告)号：US20070105329A1

公开(公告)日：2007-05-10

申请号：US11617936

申请日：2006-12-29

申请人： Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L29/76 ,  H01L21/8222

CPC分类号： H01L27/0617 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/13 ,  H01L28/10 ,  H01L28/20 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： Plural trench isolation films are provided with portions of an SOI layer interposed therebetween in a surface of the SOI layer in a resistor region (RR) where a spiral inductor (SI) is to be provided. Resistive element are formed on the trench isolation films, respectively. Each of the trench isolation films includes a central portion which passes through the SOI layer and reaches a buried oxide film to include a full-trench isolation structure, and opposite side portions each of which passes through only a portion of the SOI layer and is located on the SOI layer to include a partial-trench isolation structure. Thus, each of the trench isolation films includes a hybrid-trench isolation structure.

摘要翻译： 多个沟槽隔离膜在其中设置有螺旋电感器（SI）的电阻器区域（RR）中的SOI层的表面中设置有SOI层的部分。 电阻元件分别形成在沟槽隔离膜上。 每个沟槽隔离膜包括穿过SOI层并到达掩埋氧化膜以包括全沟槽隔离结构的中心部分，以及相对的侧部，其每个仅穿过SOI层的一部分并且位于 在SOI层上以包括部分沟槽隔离结构。 因此，每个沟槽隔离膜包括混合沟槽隔离结构。

公开(公告)号：US07187040B2

公开(公告)日：2007-03-06

申请号：US11078581

申请日：2005-03-14

申请人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Il-Jung Kim ,  Kazuhito Tsutsumi ,  Hirotada Kuriyama ,  Yoshiyuki Ishigaki ,  Motomu Ukita ,  Toshiaki Tsutsumi

发明人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Il-Jung Kim ,  Kazuhito Tsutsumi ,  Hirotada Kuriyama ,  Yoshiyuki Ishigaki ,  Motomu Ukita ,  Toshiaki Tsutsumi

IPC分类号： H01L29/76 ,  H01L31/113

CPC分类号： H01L29/78609 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78639

摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.

摘要翻译： 提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。 漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。 漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。 定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

公开(公告)号：US20060289904A1

公开(公告)日：2006-12-28

申请号：US11425072

申请日：2006-06-19

申请人： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Mikio Tsujiuchi ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L29/76

CPC分类号： H01L29/458 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/78609

摘要： In the semiconductor device which has partial trench isolation as isolation between elements formed in an SOI substrate, resistance reduction of the source drain of a transistor and reduction of leakage current are aimed at. A MOS transistor is formed in the active region specified by the isolation insulating layer in the SOI layer formed on the buried oxide film layer (BOX layer). An isolation insulating layer is a partial trench isolation which has not reached a BOX layer, and source and drain regions include the first and the second impurity ion which differs in a mass number mutually.

公开(公告)号：US20060244064A1

公开(公告)日：2006-11-02

申请号：US11448827

申请日：2006-06-08

申请人： Takashi Ipposhi ,  Toshiaki Iwamatsu

发明人： Takashi Ipposhi ,  Toshiaki Iwamatsu

IPC分类号： H01L27/12

CPC分类号： H01L29/7833 ,  H01L21/761 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665

摘要： Formed on an insulator (9) are an N− type semiconductor layer (10) having a partial isolator formed on its surface and a P− type semiconductor layer (20) having a partial isolator formed on its surface. Source/drain (11, 12) being P+ type semiconductor layers are provided on the semiconductor layer (10) to form a PMOS transistor (1). Source/drain (21, 22) being N+ type semiconductor layers are provided on the semiconductor layer (20) to form an NMOS transistor (2). A pn junction (J5) formed by the semiconductor layers (10, 20) is provided in a CMOS transistor (100) made up of the transistors (1, 2). The pn junction (J5) is positioned separately from the partial isolators (41, 42), where the crystal defect is thus very small. Therefore, the leakage current is very low at the pn junction (J5).

公开(公告)号：US07112854B1

公开(公告)日：2006-09-26

申请号：US08850631

申请日：1997-05-02

申请人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Il-Jung Kim ,  Kazuhito Tsutsumi ,  Hirotada Kuriyama ,  Yoshiyuki Ishigaki ,  Motomu Ukita ,  Toshiaki Tsutsumi

发明人： Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Il-Jung Kim ,  Kazuhito Tsutsumi ,  Hirotada Kuriyama ,  Yoshiyuki Ishigaki ,  Motomu Ukita ,  Toshiaki Tsutsumi

IPC分类号： H01L29/78

CPC分类号： H01L29/78609 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66757 ,  H01L29/78618 ,  H01L29/78624 ,  H01L29/78639

摘要： Provided are a thin-film transistor formed by connecting polysilicon layers having different conductivity types with each other which prevents occurrence of inconvenience resulting from diffusion of impurities and a method of fabricating the same. A drain (6), a channel (7) and a source (8) are integrally formed on a surface of a second oxide film (4) by polysilicon. The drain (6) is formed to be connected with a pad layer (3) (second polycrystalline semiconductor layer) through a contact hole (5) which is formed to reach an upper surface of the pad layer (3). The pad layer (3) positioned on a bottom portion of the contact hole (5) (opening) is provided with a boron implantation region BR.

摘要翻译： 提供了通过将具有不同导电类型的多晶硅层彼此连接而形成的薄膜晶体管，其防止由杂质扩散引起的不便的发生及其制造方法。 漏极（6），沟道（7）和源极（8）通过多晶硅一体地形成在第二氧化膜（4）的表面上。 漏极（6）形成为通过形成为到达焊盘层（3）的上表面的接触孔（5）与焊盘层（3）（第二多晶半导体层）连接。 定位在接触孔（5）（开口）的底部的衬垫层（3）设置有硼注入区域BR。

公开(公告)号：US07105389B2

公开(公告)日：2006-09-12

申请号：US10748273

申请日：2003-12-31

申请人： Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shigenobu Maeda ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L21/00

CPC分类号： H01L29/78615 ,  H01L21/76283 ,  H01L21/823878 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

摘要： In formation of a source/drain region of an NMOS transistor, a gate-directional extension region of an N+ block region in an N+ block resist film located under the gate-directional extension region from implantation of an N-type impurity. A high resistance forming region, which is the well region having a possibility for implantation of an N-type impurity on a longitudinal extension of a gate electrode , can be formed as a high resistance forming region narrower than a conventional high resistance forming region . Thus, a semiconductor device having a partially isolated body fixed SOI structure capable of reducing body resistance and a method of manufacturing the same are obtained.

摘要翻译： 在形成NMOS晶体管的源极/漏极区域的情况下，在N + +块区域中的N + +块区域<41>的栅极方向延伸区域 抗蚀膜<51 <防止位于栅极方向延伸区域<41a>下方的阱区11从注入N型杂质。 具有在栅电极9的纵向延伸上注入N型杂质的可能性的阱区<11>的高电阻形成区域可以形成为高电阻形成区域 比传统的高电阻形成区域窄。 因此，获得具有能够降低体电阻的部分隔离体固定的SOI结构的半导体器件及其制造方法。

公开(公告)号：US20060088963A1

公开(公告)日：2006-04-27

申请号：US11240508

申请日：2005-10-03

申请人： Takashi Ipposhi

发明人： Takashi Ipposhi

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/0847 ,  H01L21/76281 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/6656 ,  H01L29/7833

摘要： An oxide film is formed on an SOI layer, an isolation oxide film and a gate electrode. A nitride film is formed on the oxide film. Next, anisotropic etching is performed only on the nitride film to form sidewalls on opposite side surfaces of the gate electrode. Thus, the oxide film is not etched. Next, an N-type impurity is implanted through the oxide film to form source/drain regions in an upper portion of the SOI layer. In this step, adjusting the implantation energy so that the impurity reaches the buried oxide film provides the source/drain regions in contact with the buried oxide film.

摘要翻译： 在SOI层，隔离氧化膜和栅电极上形成氧化膜。 在氧化膜上形成氮化膜。 接下来，仅在氮化膜上进行各向异性蚀刻，以在栅电极的相对侧表面上形成侧壁。 因此，氧化膜不被蚀刻。 接下来，通过氧化膜注入N型杂质，以在SOI层的上部形成源/漏区。 在该步骤中，调整注入能量使得杂质到达掩埋氧化膜，使源/漏区与掩埋氧化膜接触。

公开(公告)号：US06953979B1

公开(公告)日：2005-10-11

申请号：US09466934

申请日：1999-12-20

申请人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

发明人： Yasuo Yamaguchi ,  Shigeto Maegawa ,  Takashi Ipposhi ,  Toshiaki Iwamatsu ,  Shigenobu Maeda ,  Yuuichi Hirano ,  Takuji Matsumoto ,  Shoichi Miyamoto

IPC分类号： H01L21/762 ,  H01L21/331 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786 ,  H01L31/00

CPC分类号： H01L21/84 ,  H01L27/1203

摘要： A partial oxide film (31) with well regions formed therebeneath isolates transistor formation regions in an SOI layer (3) from each other. A p-type well region (11) is formed beneath part of the partial oxide film (31) which isolates NMOS transistors from each other, and an n-type well region (12) is formed beneath part of the partial oxide film (31) which isolates PMOS transistors from each other. The p-type well region (11) and the n-type well region (12) are formed in side-by-side relation beneath part of the partial oxide film (31) which provides isolation between the NMOS and PMOS transistors. A body region is in contact with the well region (11) adjacent thereto. An interconnect layer formed on an interlayer insulation film (4) is electrically connected to the body region through a body contact provided in the interlayer insulation film (4). A semiconductor device having an SOI structure reduces a floating-substrate effect.

摘要翻译： 在其之间形成的具有阱区的部分氧化物膜（31）将SOI层（3）中的晶体管形成区域彼此隔离。 在部分氧化膜（31）的下部形成p型阱区（11），其将NMOS晶体管彼此隔离，并且在部分氧化膜（31）的一部分下方形成n型阱区（12） ），其将PMOS晶体管彼此隔离。 p型阱区（11）和n型阱区（12）在部分氧化膜（31）的下部并排形成，其提供NMOS和PMOS晶体管之间的隔离。 身体区域与与其相邻的井区域（11）接触。 形成在层间绝缘膜（4）上的互连层通过设置在层间绝缘膜（4）中的主体接触部电连接到体区。 具有SOI结构的半导体器件减少浮置衬底效应。

公开(公告)号：US06879002B2

公开(公告)日：2005-04-12

申请号：US10431473

申请日：2003-05-08

申请人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Shoichi Miyamoto ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L27/12 ,  H01L29/423 ,  H01L31/0392 ,  H01L27/01 ,  H01L29/00

CPC分类号： H01L27/1203 ,  H01L29/42384

摘要： A semiconductor device comprising an SOI substrate fabricated by forming a silicon layer 3 on an insulating layer 2, a plurality of active regions 3 horizontally arranged in the silicon layer 3, and element isolating parts 5 having a trench-like shape which is made of an insulator 5 embedded between the active regions 3 in the silicon layer 3, wherein the insulating layer 2 has spaces 6 positioned in the vicinity of interfaces between the active regions and the element isolating parts 5, whereby it becomes possible to reduce fixed charges or holes existing on a side of the insulating layer in interfaces between the silicon layer and the insulating layer, which fixed charges or holes are generated in a process of oxidation for forming the insulating layer on a bottom surface of the silicon layer.

摘要翻译： 一种半导体器件，包括通过在绝缘层2上形成硅层3，在硅层3中水平布置的多个有源区3和由沟槽状构成的沟槽状形状的元件隔离部5制造的SOI衬底 绝缘体5嵌入在硅层3中的有源区3之间，其中绝缘层2具有位于有源区和元件隔离部5之间的界面附近的空间6，从而可以减少固定电荷或孔 在硅层和绝缘层之间的界面中的绝缘层的一侧上，在硅层的底表面上形成绝缘层的氧化过程中产生固定的电荷或空穴。

公开(公告)号：US06869865B2

公开(公告)日：2005-03-22

申请号：US10608154

申请日：2003-06-30

申请人： Shigeto Maegawa ,  Takashi Ipposhi ,  Kazunobu Ohta ,  Yasuo Inoue ,  Masanobu Kohara ,  Takashi Eura ,  Natsuro Tsubouchi

发明人： Shigeto Maegawa ,  Takashi Ipposhi ,  Kazunobu Ohta ,  Yasuo Inoue ,  Masanobu Kohara ,  Takashi Eura ,  Natsuro Tsubouchi

IPC分类号： H01L21/28 ,  H01L21/20 ,  H01L21/265 ,  H01L21/268 ,  H01L21/285 ,  H01L21/336 ,  H01L29/78 ,  H01L21/425

CPC分类号： H01L21/268 ,  H01L21/2652 ,  H01L21/28518 ,  H01L29/6659

摘要： Activation of impurities is achieved without involving creation of a crystal defect or deformation by using phonon absorption. A laser beam (42) having a wavelength in a range of 16 to 17 μm is irradiated onto silicon, to cause phonon absorption. Before an energy supplied from the laser beam (42) diffuses around a portion which is irradiated with the laser beam (42), solid phase epitaxy in the portion finishes. Accordingly, crystallization occurs only in the portion which is irradiated with the laser beam (42), and does not occur in a portion which is not irradiated with the laser beam (42). Hence, heat is not excessively absorbed. Also, local phase change such as melting and solidification is not caused.

摘要翻译： 实现杂质的活化而不涉及通过使用声子吸收产生晶体缺陷或变形。 将具有16至17μm波长范围的激光束（42）照射到硅上以引起声子吸收。 在从激光束（42）供给的能量在激光束（42）的一部分附近扩散之前，该部分的固相外延结束。 因此，仅在被激光束（42）照射的部分中发生结晶，不会发生在不被激光束（42）照射的部分。 因此，热量不会被过度吸收。 此外，不会引起局部相变，如熔化和凝固。