公开(公告)号：US20200177288A1

公开(公告)日：2020-06-04

申请号：US16697236

申请日：2019-11-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sandeep Oswal ,  Visvesvaraya Pentakota ,  Jagannathan Venkataraman ,  Jaiganesh Balakrishnan ,  Francesco Dantoni

IPC: H04B17/13 ,  H04L27/36 ,  H04B1/04

Abstract: A transmitter for an RF communications system, that includes an auxiliary receiver for capturing transmit signal data for use in compensating/correcting transmit signal impairments (such as for DPD, QMC, LOL). The transmitter (such as Zero IF) includes analog chain elements that introduce transmit signal impairments (such as PA nonlinearities). The auxiliary receiver is configured to receive loopback transmit RF signals, and includes an RF direct sampling ADC to convert the loopback transmit RF signals to digital transmit RF signals. Digital down conversion circuitry is configured to downconvert the digital transmit RF signals to captured digital transmit baseband signals, and data capture circuitry is configured to generate the transmit signal data based on the captured digital transmit baseband signals.

公开(公告)号：US10666293B2

公开(公告)日：2020-05-26

申请号：US15960591

申请日：2018-04-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal Tangudu ,  Suvam Nandi ,  Jaiganesh Balakrishnan

IPC: H03M7/00 ,  H03M7/30 ,  H03H17/06 ,  H03D7/16

Abstract: A digital down converter includes a low resolution mixer, a decimation filter, and a high resolution mixer. The low resolution mixer is configured to receive a digitized radio frequency signal, and apply a first down conversion to the radio frequency signal to produce an intermediate frequency signal. The decimation filter is coupled to the low resolution mixer. The decimation filter is configured to receive the intermediate frequency signal, and reduce a sampling rate of the intermediate frequency signal to produce a decimated intermediate frequency signal. The high resolution mixer is coupled to the decimation filter. The high resolution mixer is configured to receive the decimated intermediate frequency signal, and apply a second down conversion to the decimated intermediate frequency signal to produce a down converted signal.

公开(公告)号：US20190317731A1

公开(公告)日：2019-10-17

申请号：US16454369

申请日：2019-06-27

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal Tangudu ,  Suvam Nandi ,  Pooja Sundar ,  Jaiganesh Balakrishnan

IPC: G06F7/523 ,  G06F7/50 ,  H03D7/16

Abstract: A multiplier circuit includes a partial product generation circuit, a truncation circuit, and a summation circuit. The partial product generation circuit is configured to generate a plurality of partial products for multiplying two values. The truncation circuit is coupled to the partial product generation circuit. The truncation circuit is configured to shorten at least some of the partial products by removing a least significant bit from the at least some of the partial products. The summation circuit coupled to the truncation circuit. The summation circuit is configured to sum the truncated partial products produced by the truncation circuit.

公开(公告)号：US20190280675A1

公开(公告)日：2019-09-12

申请号：US16351357

申请日：2019-03-12

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jawaharlal Tangudu ,  Jaiganesh Balakrishnan

IPC: H03H17/06 ,  H03H17/02 ,  H03H15/00

Abstract: A zero-insertion FIR filter architecture for filtering a signal with a target band and a secondary band. Digital filter circuitry includes an L-tap FIR (finite impulse response) filter, with a number L filter tap elements (L=0, 1, 2, . . . (L−1)), each with an assigned coefficient from a defined coefficient sequence. The L-tap FIR filter is configurable with a defined zero-insertion coefficient sequence of a repeating sub-sequence of a nonzero coefficient followed by one or more zero-inserted coefficients, with a number Nj of nonzero coefficients, and a number Nk of zero-inserted coefficients, so that L=Nj+Nk. The L-tap FIR filter is configurable as an M-tap FIR filter with a nonzero coefficient sequence in which each of the L filter tap elements is assigned a non-zero coefficient, the M-tap FIR filter having an effective length of M=(Nj+Nk) non-zero coefficients.

公开(公告)号：US20190068238A1

公开(公告)日：2019-02-28

申请号：US15934946

申请日：2018-03-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sarma Sundareswara Gunturi ,  Jaiganesh Balakrishnan

IPC: H04B1/66 ,  H04B1/62 ,  H04B1/04 ,  H03M7/30

Abstract: Signal compression for serialized data bandwidth reduction based on decomposition of a data signal into separate signal components with different SQNR or dynamic range requirements, and quantizing the signal components with different bit precisions. Compression logic decomposes the input data signal into the first/second signal components, quantizes the first component with a pre-defined first bit precision to provide a first quantized data signal, quantizes the second component with a pre-defined second bit precision to provide a second quantized data signal, the second bit precision less than the first bit precision, the first and second quantized data signals bit packed into a compressed digital data signal. At the receive-end, decompression logic bit unpacks the compressed digital data signal into the first/second quantized data signals, and filters/combines the first/second quantized data signals into a decompressed data signal corresponding to the input data signal including the first and second signal components.

公开(公告)号：US20180367169A1

公开(公告)日：2018-12-20

申请号：US16110478

申请日：2018-08-23

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh Balakrishnan ,  Suvam Nandi ,  Sundarrajan Rangachari

IPC: H04B1/00 ,  H04B1/10 ,  H04B1/04 ,  G06F5/01 ,  H03H17/06 ,  H03H17/02

CPC classification number: H04B1/0042 ,  G06F5/01 ,  H03H17/0211 ,  H03H17/0273 ,  H03H17/0275 ,  H03H17/0657 ,  H03H17/0664 ,  H04B1/0046 ,  H04B1/0475 ,  H04B1/1027

Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.

公开(公告)号：US20180191383A1

公开(公告)日：2018-07-05

申请号：US15395135

申请日：2016-12-30

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh Balakrishnan ,  Suvam Nandi ,  Sundarrajan Rangachari

IPC: H04B1/00 ,  H04B1/04 ,  H04B1/10 ,  G06F5/01 ,  H03H17/02

CPC classification number: H04B1/0042 ,  G06F5/01 ,  H03H17/0211 ,  H03H17/0275 ,  H03H17/0657 ,  H03H17/0664 ,  H04B1/0046 ,  H04B1/0475 ,  H04B1/1027

Abstract: A digital filter for interpolation or decimation and a device incorporating the digital filter is disclosed. The digital filter includes a filter block, a first transformation circuit coupled to the filter block and an input stream coupled to provide input values to a component selected from the filter block and the first transformation circuit. The filter block includes a pair of sub-filters having respective transformed coefficients, the respective transformed coefficients of a first sub-filter of the pair of sub-filters being symmetric and the respective transformed coefficients of a second sub-filter of the pair of sub-filters being anti-symmetric. The first transformation circuit is coupled to perform a first transformation; the filter block and the first transformation circuit together provide suppression of undesired spectral images in final outputs of the digital filter.

公开(公告)号：US09900205B2

公开(公告)日：2018-02-20

申请号：US14693416

申请日：2015-04-22

Applicant: Texas Instruments Incorporated

Inventor： Raghu Ganesan ,  Bijoy Bhukania ,  Jaiganesh Balakrishnan

IPC: H03D3/00 ,  H04L27/38 ,  H04B1/00

CPC classification number: H04L27/3863 ,  H04B1/0039

Abstract: Apparatus and methods disclosed herein perform gain, clipping, and phase compensation in the presence of I/Q mismatch in quadrature RF receivers. Gain and phase mismatch are exacerbated by differences in clipping between I & Q signals in low resolution ADCs. Signals in the stronger channel arm are clipped differentially more than weaker signals in the other channel arm. Embodiments herein perform clipping operations during iterations of gain mismatch calculations in order to balance clipping between the I and Q channel arms. Gain compensation coefficients are iteratively converged, clipping levels are established, and data flowing through the network is gain and clipping compensated. A compensation phase angle and phase compensation coefficients are then determined from gain and clipping compensated sample data. The resulting phase compensation coefficients are applied to the gain and clipping corrected receiver data to yield a gain, clipping, and phase compensated data stream.

公开(公告)号：US20180035375A1

公开(公告)日：2018-02-01

申请号：US15727891

申请日：2017-10-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh Balakrishnan ,  Sarma Sundareswara Gunturi

IPC: H04W52/02 ,  H04B1/16 ,  H04L27/26 ,  H04W84/12

CPC classification number: H04W52/0232 ,  H04B1/16 ,  H04L27/2656 ,  H04L27/2663 ,  H04W52/0229 ,  H04W84/12 ,  Y02D70/142 ,  Y02D70/144

Abstract: The disclosure provides a low power receiver. The receiver includes a first channel that receives an RF signal and generates an input signal. The receiver also includes a second channel and a packet detection circuit. The packet detection circuit is coupled to the first channel and the second channel. The packet detection circuit detects a valid packet in the input signal, and activates the second channel on detection of the valid packet.

公开(公告)号：US20180019732A1

公开(公告)日：2018-01-18

申请号：US15645647

申请日：2017-07-10

Applicant: Texas Instruments Incorporated

Inventor： Jaiganesh Balakrishnan ,  Sthanunathan Ramakrishnan ,  Pooja Sundar ,  Sashidharan Venkatraman

IPC: H03H17/02 ,  G06F7/544 ,  H03H17/00 ,  G06F5/01 ,  H03M1/12

CPC classification number: H03H17/0219 ,  G06F5/01 ,  G06F7/5443 ,  H03H17/0045 ,  H03H17/06 ,  H03M1/0626 ,  H03M1/12 ,  H03M1/1215

Abstract: In accordance with an example, an integrated circuit includes a linear combiner having an input for receiving a signal. The linear combiner also has a plurality of operator circuits for applying weighting factors to the signal, in which a first operator circuit in the plurality of operator circuits performs a first operation on the signal using a first sub-weight of one of the weighting factors to provide a first tile output and a second operator circuit in the plurality of operator circuits performs a second operation on the signal using a second sub-weight of the one of the weighting factors to provide a second tile output. The linear combiner also has an adder having a first input coupled to receive the first tile output and the second tile outputs and providing a combined output.