Method of Forming Spacers That Provide Enhanced Protection for Gate Electrode Structures
    81.
    发明申请
    Method of Forming Spacers That Provide Enhanced Protection for Gate Electrode Structures 有权
    形成对栅极电极结构提供增强保护的间隔物的方法

    公开(公告)号:US20120292671A1

    公开(公告)日:2012-11-22

    申请号:US13108363

    申请日:2011-05-16

    IPC分类号: H01L21/3213 H01L29/78

    摘要: Disclosed herein is a method of forming a semiconductor device. In one example, the method comprises forming a gate electrode structure above a semiconducting substrate and forming a plurality of spacers proximate the gate electrode structures, wherein the plurality of spacers comprises a first silicon nitride spacer positioned adjacent a sidewall of the gate electrode structure, a generally L-shaped silicon nitride spacer positioned adjacent the first silicon nitride spacer, and a silicon dioxide spacer positioned adjacent the generally L-shaped silicon nitride spacer.

    摘要翻译: 本文公开了形成半导体器件的方法。 在一个示例中,该方法包括在半导体衬底之上形成栅电极结构并在栅电极结构附近形成多个间隔区,其中多个间隔物包括邻近栅电极结构的侧壁定位的第一氮化硅间隔区, 位于第一氮化硅间隔物附近的通常为L形的氮化硅间隔物,和位于大致L形的氮化硅间隔物附近的二氧化硅隔离物。

    Enhanced etch stop capability during patterning of silicon nitride including layer stacks by providing a chemically formed oxide layer during semiconductor processing
    82.
    发明授权
    Enhanced etch stop capability during patterning of silicon nitride including layer stacks by providing a chemically formed oxide layer during semiconductor processing 有权
    通过在半导体处理期间提供化学形成的氧化物层,在包括层堆叠的氮化硅图案化期间增强蚀刻停止能力

    公开(公告)号:US08283232B2

    公开(公告)日:2012-10-09

    申请号:US12785849

    申请日:2010-05-24

    IPC分类号: H01L21/336

    摘要: A gate electrode structure may be formed on the basis of a silicon nitride cap material in combination with a very thin yet uniform silicon oxide based etch stop material, which may be formed on the basis of a chemically driven oxidation process. Due to the reduced thickness, a pronounced material erosion, for instance, during a wet chemical cleaning process after gate patterning, may be avoided, thereby not unduly affecting the further processing, for instance with respect to forming an embedded strain-inducing semiconductor alloy, while nevertheless providing the desired etch stop capabilities during removing the silicon nitride cap material.

    摘要翻译: 栅极电极结构可以基于氮化硅帽材料与非常薄且均匀的基于氧化硅的蚀刻停止材料组合形成,其可以基于化学驱动的氧化工艺形成。 由于厚度减小,可以避免例如在门图案化之后的湿化学清洁过程期间显着的材料侵蚀,从而不会过度影响进一步的加工,例如关于形成嵌入式应变诱导半导体合金, 同时在去除氮化硅帽材料期间提供期望的蚀刻停止能力。

    Enhanced Patterning Uniformity of Gate Electrodes of a Semiconductor Device by Late Gate Doping
    83.
    发明申请
    Enhanced Patterning Uniformity of Gate Electrodes of a Semiconductor Device by Late Gate Doping 有权
    通过晚期栅极掺杂增强半导体器件的栅极电极的图案化均匀性

    公开(公告)号:US20120156865A1

    公开(公告)日:2012-06-21

    申请号:US13189997

    申请日:2011-07-25

    IPC分类号: H01L21/28

    摘要: When forming sophisticated semiconductor-based gate electrode structures of transistors, the pre-doping of one type of gate electrode structure may be accomplished after the actual patterning of the electrode material by using an appropriate mask or fill material for covering the active regions and using a lithography mask. In this manner, a high degree of flexibility is provided with respect to selecting an appropriate patterning regime, while at the same time a uniform and superior cross-sectional shape for any type of gate electrode structure is obtained.

    摘要翻译: 当形成晶体管的复杂的基于半导体的栅极电极结构时,一种类型的栅极电极结构的预掺杂可以在通过使用适当的掩模或填充材料覆盖活性区域并使用 光刻面具 以这种方式,在选择适当的图案化状态方面提供了高度的柔性,同时获得了任何类型的栅电极结构的均匀和优异的横截面形状。

    PERFORMANCE ENHANCEMENT IN PFET TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY INCREASING DOPANT CONFINEMENT
    88.
    发明申请
    PERFORMANCE ENHANCEMENT IN PFET TRANSISTORS COMPRISING HIGH-K METAL GATE STACK BY INCREASING DOPANT CONFINEMENT 有权
    通过增加DOPANT约定包含高K金属栅极堆叠的PFET晶体管的性能增强

    公开(公告)号:US20110127618A1

    公开(公告)日:2011-06-02

    申请号:US12905383

    申请日:2010-10-15

    IPC分类号: H01L29/78 H01L21/336

    摘要: In a P-channel transistor comprising a high-k metal gate electrode structure, a superior dopant profile may be obtained, at least in the threshold adjusting semiconductor material, such as a silicon/germanium material, by incorporating a diffusion blocking species, such as fluorine, prior to forming the threshold adjusting semiconductor material. Consequently, the drain and source extension regions may be provided with a high dopant concentration as required for obtaining the target Miller capacitance without inducing undue dopant diffusion below the threshold adjusting semiconductor material, which may otherwise result in increased leakage currents and increased risk of punch through events.

    摘要翻译: 在包含高k金属栅电极结构的P沟道晶体管中,至少在阈值调节半导体材料(例如硅/锗材料)中可以通过掺入扩散阻挡物质获得优异的掺杂剂分布,例如 在形成阈值调节半导体材料之前。 因此,漏极和源极延伸区域可以被提供有高的掺杂剂浓度,以获得目标米勒电容,而不会导致低于阈值调节半导体材料的不适当的掺杂剂扩散,否则可能导致增加的漏电流和增加的穿孔风险 事件