公开(公告)号：US08266552B2

公开(公告)日：2012-09-11

申请号：US12705640

申请日：2010-02-15

申请人： Takafumi Taguchi ,  Toshiya Kotani ,  Michiya Takimoto ,  Fumiharu Nakajima ,  Ryota Aburada ,  Hiromitsu Mashita ,  Katsumi Iyanagi ,  Chikaaki Kodama

发明人： Takafumi Taguchi ,  Toshiya Kotani ,  Michiya Takimoto ,  Fumiharu Nakajima ,  Ryota Aburada ,  Hiromitsu Mashita ,  Katsumi Iyanagi ,  Chikaaki Kodama

IPC分类号： G06F17/50 ,  G06F19/00 ,  G05B13/04

CPC分类号： G03F1/36

摘要： Pattern formation simulations are performed based on design layout data subjected to OPC processing with a plurality of process parameters set in process conditions. A worst condition of the process conditions is calculated based on risk points extracted from simulation results. The design layout data or the OPC processing is changed such that when a pattern is formed under the worst condition based on the changed design layout data or the changed OPC processing a number of the risk points or a risk degree of the risk points of the pattern is smaller than the simulation result.

摘要翻译： 基于在处理条件下设置的多个处理参数进行OPC处理的设计布局数据来执行模式形成模拟。 根据模拟结果提取的风险点计算过程条件的最差条件。 改变设计布局数据或OPC处理，使得当在最坏条件下基于改变的设计布局数据形成图案时，或者改变的OPC处理多个风险点或图案的风险点的风险程度 小于模拟结果。

公开(公告)号：US20120047475A1

公开(公告)日：2012-02-23

申请号：US13285650

申请日：2011-10-31

申请人： Toshiya Kotani

发明人： Toshiya Kotani

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  H01J2237/31769

摘要： A semiconductor device is provided having a physical pattern based on a designed pattern, the designed pattern including a target pattern and a correction pattern designed for a pattern to be formed on a wafer; the target pattern includes a first portion of an edge with a first distance, a second portion of the edge with a second distance, which is different from the first distance, and a third portion of the edge having a first region of the edge with the first distance and a second region of the edge with the second distance; and the correction pattern is added to at least one of the first portion, the second portion, and the third portion such that the first portion, the second portion, and the third portion are caused to differ from one another in dimensions of the designed pattern.

摘要翻译： 提供具有基于设计图案的物理图案的半导体器件，所设计的图案包括针对要在晶片上形成的图案设计的目标图案和校正图案; 目标图案包括具有第一距离的边缘的第一部分，具有第二距离的边缘的第二部分，其不同于第一距离，并且边缘的第三部分具有边缘的第一区域，其具有 第一距离和具有第二距离的边缘的第二区域; 并且将修正图案添加到第一部分，第二部分和第三部分中的至少一个，使得第一部分，第二部分和第三部分在设计图案的尺寸上彼此不同 。

公开(公告)号：US08112167B2

公开(公告)日：2012-02-07

申请号：US12354574

申请日：2009-01-15

申请人： Ayako Endo ,  Kenji Yoshida ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Ayako Endo ,  Kenji Yoshida ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F19/00 ,  G06F17/50

CPC分类号： G05B19/41865 ,  G05B19/41885 ,  H01L22/20 ,  H01L2924/0002 ,  Y02P90/20 ,  Y02P90/26 ,  H01L2924/00

摘要： A process control method comprises adjusting a process condition in consideration of a performance variation among a plurality of manufacturing apparatuses, the performance variation affecting a finished shape of a pattern used to manufacture a semiconductor device, running a simulation of the finished shape under the adjusted process condition, extracting a dangerous point of the pattern affecting satisfaction from the result of the simulation, comparing a first process capability serving as a judgment standard to find whether a production schedule of the device is achieved with a second capability serving to form a dangerous pattern containing the dangerous point, and improving the second process when the second process capability is lower than the first process capability.

摘要翻译： 一种过程控制方法包括考虑多个制造装置之间的性能变化来调整工艺条件，影响用于制造半导体器件的图案的成品形状的性能变化，在调整过程下运行成品形状的模拟 从模拟结果中提取影响满意度的模式的危险点，比较作为判断标准的第一处理能力，以确定是否实现具有第二能力的设备的生产计划，以形成含有 危险点，并且当第二处理能力低于第一处理能力时，改进第二过程。

公开(公告)号：US08101516B2

公开(公告)日：2012-01-24

申请号：US11857275

申请日：2007-09-18

申请人： Toshiya Kotani ,  Hiroko Nakamura ,  Koji Hashimoto

发明人： Toshiya Kotani ,  Hiroko Nakamura ,  Koji Hashimoto

IPC分类号： H01L21/4763

CPC分类号： H01L21/31144 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76816

摘要： A block film is formed on a region which includes a region of an insulating layer where a first hole is to be formed, and in which no second hole is to be formed, and a resist film having openings for forming the first and second holes is formed on the block film and insulating layer. Etching is performed by using the resist film as a mask, thereby forming the first hole in the block film and insulating layer, and the second hole in the insulating layer. The depth of the first hole from the upper surface of the insulating layer is smaller than that of the second hole, so the first hole does not reach the semiconductor substrate.

摘要翻译： 在包括要形成第一孔的绝缘层的区域，并且不形成第二孔的区域上形成阻挡膜，并且具有用于形成第一孔和第二孔的开口的抗蚀剂膜是 形成在阻挡膜和绝缘层上。 通过使用抗蚀剂膜作为掩模进行蚀刻，从而在阻挡膜和绝缘层中形成第一孔，并在绝缘层中形成第二孔。 绝缘层的上表面的第一孔的深度小于第二孔的深度，所以第一孔不到达半导体衬底。

公开(公告)号：US07996794B2

公开(公告)日：2011-08-09

申请号：US11945697

申请日：2007-11-27

申请人： Sachiko Kobayashi ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

发明人： Sachiko Kobayashi ,  Toshiya Kotani ,  Shinichiroh Ohki ,  Hirotaka Ichikawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： Disclosed is a mask data processing method of correcting a hierarchical structure. In the case that in design data having a hierarchical structure including a plurality of cells each having a design pattern, when the total number of graphic forms or the total edge length of a design pattern on which the calculation of mask data processing is to be executed, the amount of calculation to be executed, or the expansion degree presumably becomes equal to or larger than a predetermined threshold value if the calculation of the mask data processing is executed on the design data having the initial hierarchical structure, the hierarchical structure is corrected. This correction is performed to reduce the total number of graphic forms or the total edge length of the design pattern on which the calculation is to be executed, the amount of calculation to be executed, of the expansion degree.

摘要翻译： 公开了一种校正层次结构的掩模数据处理方法。 在具有包括多个单元的设计数据的设计数据中，每个单元均具有设计图案时，当要执行掩模数据处理的计算的设计图案的总数或总边沿长度时 如果对具有初始层次结构的设计数据执行掩模数据处理的计算，则修正了要执行的计算量或扩展度等于或大于预定阈值等于或大于预定阈值。 执行该校正以减少要执行计算的设计模式的总数或总边缘长度，即要执行的计算量，扩展度。

公开(公告)号：US20100202181A1

公开(公告)日：2010-08-12

申请号：US12561531

申请日：2009-09-17

申请人： Takaki HASHIMOTO ,  Hidefumi Mukai ,  Yasunobu Kai ,  Toshiya Kotani

发明人： Takaki HASHIMOTO ,  Hidefumi Mukai ,  Yasunobu Kai ,  Toshiya Kotani

IPC分类号： G11C5/06

CPC分类号： G11C5/063 ,  G11C5/025

摘要： A semiconductor memory device includes a semiconductor substrate on which memory cells are formed. Interconnects are arranged along a first direction above the semiconductor substrate, and have regular intervals along a second direction perpendicular to the first direction. Interconnect contacts connect the interconnects and the semiconductor substrate, are arranged on three or more rows. The center of each of two of the interconnect contacts which are connected to the interconnects adjacent in the second direction deviate from each other along the first direction.

摘要翻译： 半导体存储器件包括形成有存储单元的半导体衬底。 互连件沿着半导体衬底上方的第一方向布置，并且沿着垂直于第一方向的第二方向具有规则的间隔。 互连触点连接互连和半导体衬底，布置在三行或更多行上。 连接到在第二方向相邻的互连件的两个互连触点中的每一个的中心沿着第一方向彼此偏离。

公开(公告)号：US20100193960A1

公开(公告)日：2010-08-05

申请号：US12659773

申请日：2010-03-22

申请人： Hiromitsu Mashita ,  Toshiya Kotani ,  Atsushi Maesono ,  Ayako Nakano ,  Tadahito Fujisawa

发明人： Hiromitsu Mashita ,  Toshiya Kotani ,  Atsushi Maesono ,  Ayako Nakano ,  Tadahito Fujisawa

IPC分类号： H01L23/52 ,  G06F17/50 ,  G03F1/00

CPC分类号： H01L27/0207 ,  G03F1/00 ,  G03F1/36 ,  G06F17/5068 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11519

摘要： A semiconductor device includes a semiconductor substrate, and a circuit pattern group comprising at least N (≧2) circuit pattern on the semiconductor substrate, at least one vicinity of end portion among the at least of N circuit patterns including a connection area to electrically connect to a circuit pattern in another circuit pattern group different from the circuit pattern group, the at least N wirings pattern including a circuit pattern N1 and at least one circuit pattern Ni (i≧2) arranged in one direction different from longitudinal direction of the circuit pattern N1, the at least one circuit patterns Ni having larger i being arranged at further position away from the circuit pattern N1, and in terms of a pattern including the connection area among the at least of Ni circuit patterns, the larger the i, the connection area being arranged at a further position in longitudinal direction.

摘要翻译： 半导体器件包括半导体衬底和在半导体衬底上至少包括N（≥2）个电路图案的电路图案组，至少N个电路图案中的至少一个端部附近包括连接区域以电连接 涉及与电路图案组不同的另一个电路图案组中的电路图案，所述至少N个布线图案包括电路图案N1和沿与电路的纵向方向不同的一个方向布置的至少一个电路图案Ni（i≥2） 图案N1中，具有较大i的至少一个电路图案Ni布置在远离电路图案N1的更远位置处，并且根据包括至少Ni电路图案中的连接区域的图案，i， 连接区域布置在纵向方向上的另一位置。

公开(公告)号：US20100082144A1

公开(公告)日：2010-04-01

申请号：US12554495

申请日：2009-09-04

申请人： Masanori TAKAHASHI ,  Toshiya Kotani ,  Satoshi Tanaka

发明人： Masanori TAKAHASHI ,  Toshiya Kotani ,  Satoshi Tanaka

IPC分类号： G06F19/00 ,  G06F17/50

CPC分类号： G06F17/5081

摘要： Method of calculating pattern-failure-occurrence-region comprising calculating a pattern failure occurrence region using relation information and a layout used for forming a convex section, the relation information being a relation between a distance from a formed pattern in a film to cover the convex section on a substrate to the convex section and a region in the film in which a shape of the formed pattern cannot satisfy a predetermined condition because of influence of the convex section.

摘要翻译： 计算图案故障发生区域的方法包括使用关系信息和用于形成凸部的布局来计算图案故障发生区域，所述关系信息是从胶片中形成的图案到覆盖凸起的距离之间的关系 由于凸部的影响，形成图案的形状不能满足规定条件的膜中的与凸部的基板上的区域。

公开(公告)号：US20090258446A1

公开(公告)日：2009-10-15

申请号：US12420931

申请日：2009-04-09

申请人： Toshiya Kotani ,  Hiromitsu Mashita ,  Kazuhito Kobayashi

发明人： Toshiya Kotani ,  Hiromitsu Mashita ,  Kazuhito Kobayashi

IPC分类号： H01L21/66 ,  G01B15/00

CPC分类号： G03F1/36 ,  G03F1/68

摘要： A pattern verification method according to an embodiment includes, dividing a pattern data region or a pattern formation region formed based on the pattern data to a plurality of unit regions, calculating a pattern area ratio with respect to each unit region, calculating differences in the amount of the pattern area ratio between each unit region and adjacent unit regions thereto, setting the number or density of measurement point with respect to each unit region to the pattern of the pattern data region or the pattern formation region according to the difference in the amount of pattern area ratio, measuring the pattern size at each measurement point, and verifying whether the size measurement value is within a predetermined range or not.

摘要翻译： 根据实施例的图案验证方法包括：将基于图案数据形成的图案数据区域或图案形成区域划分为多个单位区域，计算相对于每个单位区域的图案面积比，计算量的差异 每个单位区域与相邻单位区域之间的图案面积比率，将测量点的数量或密度相对于每个单位区域设置为图案数据区域或图案形成区域的图案，根据 测量每个测量点处的图案尺寸，以及验证尺寸测量值是否在预定范围内。

公开(公告)号：US07585597B2

公开(公告)日：2009-09-08

申请号：US11259069

申请日：2005-10-27

申请人： Tadahito Fujisawa ,  Takeshi Ito ,  Toshiya Kotani

发明人： Tadahito Fujisawa ,  Takeshi Ito ,  Toshiya Kotani

IPC分类号： G03F1/00

CPC分类号： G03F7/70441 ,  G03F1/36

摘要： A mask pattern data generating method is disclosed, which comprises preparing mask pattern data which corresponds to a design pattern including a pair of line patterns formed of two line patterns, and disposing an auxiliary pattern which is un-transferable to a resist film at a center of a space region between the pair of line patterns, in which the disposing of the auxiliary pattern includes obtaining a shape of the auxiliary pattern which meets formulae in which a width in the short edge direction of the auxiliary pattern, a space width between the auxiliary pattern and one of the pair of line patterns, a wavelength of an exposure light emitted by a projection aligner using a photo mask at exposure, and a numerical apertures of a projection lens of the projection aligner are defined as parameters, and disposing the obtained auxiliary pattern at the center of the space region.

摘要翻译： 公开了一种掩模图案数据生成方法，其包括制备对应于包括由两条线图案形成的一对线图案的设计图案的掩模图案数据，并且将不可转印到辅助图案的抗蚀剂膜设置在中心 在一对线图案之间的空间区域中，其中辅助图案的设置包括获得辅助图案的形状，其满足辅助图案的短边方向上的宽度，辅助图案的短边方向之间的空间宽度 图案和一对线图案中的一个，曝光时由使用光掩模的投影对准器发射的曝光光的波长和投影对准器的投影透镜的数值孔径被定义为参数，并且将所获得的辅助 模式在空间区域的中心。