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147 条记录 (耗时 0.028 秒)

    Picture reproduction apparatus and picture decoding apparatus
    81.
    发明授权
    Picture reproduction apparatus and picture decoding apparatus 失效
    图像再现装置和图像解码装置

    公开(公告)号：US5649047A

    公开(公告)日：1997-07-15

    申请号：US254037

    申请日：1994-06-03

    申请人： Toshiya Takahashi ,  Tatsushi Bannai

    发明人： Toshiya Takahashi ,  Tatsushi Bannai

    IPC分类号： H04N5/783 ,  H04N5/926 ,  H04N5/92

    CPC分类号： H04N5/783 ,  H04N5/9264 ,  H04N5/9261

    摘要： The picture reproduction apparatus of this invention reproduces compressed image data which has been compressed using inter-frame encoding, extracts a header from the reproduced image data, taking out intra-frame encoded image data using the information of the header. Invalid data is added to the image data other than the intra-frame encoded data. The image data is output into a picture decoding apparatus, so as to obtain a reproduced video image during playback in fast forward and fast reverse. Alternatively, valid image data is detected from the reproduced image data. In the slow playback at a 1/N speed, M (

    摘要翻译： 本发明的图像再现设备使用帧间编码再现已经压缩的压缩图像数据，从再现的图像数据中提取标题，使用报头的信息取出帧内编码的图像数据。 将无效数据添加到图像数据之外，而不是帧内编码数据。 将图像数据输出到图像解码装置中，以便在快进和快退过程中获得再现的视频图像。 或者，从再现的图像数据检测有效图像数据。 在1 / N速度的慢播放中，输出有效图像数据的M（

    Image coding method and apparatus
    85.
    发明授权
    Image coding method and apparatus 失效
    图像编码方法及装置

    公开(公告)号：US5347309A

    公开(公告)日：1994-09-13

    申请号：US871697

    申请日：1992-04-21

    申请人： Toshiya Takahashi

    发明人： Toshiya Takahashi

    IPC分类号： G06T9/00 ,  H04N7/26 ,  H04N7/36 ,  H04N7/50 ,  H04N7/137

    CPC分类号： H04N19/527 ,  H04N19/105 ,  H04N19/112 ,  H04N19/137 ,  H04N19/51 ,  H04N19/61

    摘要： An inter-field motion vector of an interlaced scanned inputted image is detected, and, using the detected inter-field motion vector, movements between fields are compensated to constitute a frame. The frame is then subjected to block coding. Alternatively, an interlaced scanned input image is subjected to two-dimensional block division and further an activity of each two-dimensional block is calculated. Using the activity as an index, the two-dimensional block is divided into either field small blocks constituted by field data or frame small blocks constituted by frame data, and the divided small blocks are coded. By these steps, even an image having large motion does not invite degradation of image quality, and high efficiency image coding can be realized.

    摘要翻译： 检测隔行扫描的输入图像的场间运动矢量，并且使用检测到的场间运动矢量来补偿场之间的运动以构成帧。 然后对该帧进行块编码。 或者，将隔行扫描的输入图像进行二维块划分，并且还计算每个二维块的活动。 使用活动作为索引，二维块被划分为由场数据构成的场小块或由帧数据构成的帧小块，并且分割的小块被编码。 通过这些步骤，即使具有大的运动的图像也不会引起图像质量的劣化，并且可以实现高效率的图像编码。

    Rounding unit for use in arithmetic processing of floating point data
    90.
    发明授权
    Rounding unit for use in arithmetic processing of floating point data 失效
    用于浮点数据算术处理的舍入单元

    公开(公告)号：US4796217A

    公开(公告)日：1989-01-03

    申请号：US754102

    申请日：1985-07-12

    申请人： Toshiya Takahashi ,  Junichi Iwasaki

    发明人： Toshiya Takahashi ,  Junichi Iwasaki

    IPC分类号： G06F7/38 ,  G06F7/00 ,  G06F7/48 ,  G06F7/483 ,  G06F7/508 ,  G06F7/57

    CPC分类号： G06F7/483 ,  G06F7/48 ,  G06F7/49947

    摘要： A rounding unit for use in arithmetic processing of register floating point data. The rounding unit comprises a mantissa part register for storing the mantissa part of the floating point data, an exponent part register for storing the exponent part of the floating point data, a judging circuit for judging whether the rounding operation is raising or truncating, a mantissa part incrementer for incrementing the mantissa part of the floating point data and outputting a carry signal when it is overflowed, an exponent part incrementer for incrementing the exponent part of the floating point data and a selection circuit which, in response to the carry signal from the mantissa part incrementer and the judging signal from the judging circuit, orders the mantissa part register to store a constant data of which the most significant bit is "1" and the other bits are "0", when the rounding operation is raising and the carry signal is present. For generating the constant data, a constant register or an adjusting means is employed. The rounding unit executes the rounding operation of floating point data by hardware and thus it operates at a very high speed.

    摘要翻译： 用于寄存器浮点数据的算术处理的舍入单元。 四舍五入单元包括用于存储浮点数据的尾数部分的尾数部分寄存器，用于存储浮点数据的指数部分的指数部分寄存器，用于判断舍入操作是上升还是截断的判断电路，尾数 用于递增浮点数据的尾数部分并在其溢出时输出进位信号的部分增量器，用于递增浮点数据的指数部分的指数部分递增器和响应于来自该浮点数据的进位信号的选择电路 尾数部分增量器和判断电路的判断信号，命令尾数部分寄存器存储最高有效位为“1”的常数数据，其他位为“0”，当舍入操作提升时，进位 信号存在。 为了产生常数数据，采用常数寄存器或调整装置。 舍入单元通过硬件执行浮点数据的舍入运算，从而以非常高的速度运行。