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196 条记录 (耗时 0.052 秒)

    Split-polysilicon CMOS process incorporating unmasked punchthrough and source/drain implants
    81.
    发明授权
    Split-polysilicon CMOS process incorporating unmasked punchthrough and source/drain implants 失效
    分裂多晶硅CMOS工艺结合未屏蔽的穿透和源/漏植入

    公开(公告)号：US5032530A

    公开(公告)日：1991-07-16

    申请号：US427639

    申请日：1989-10-27

    申请人： Tyler A. Lowrey ,  Randal W. Chance ,  Ward D. Parkinson

    发明人： Tyler A. Lowrey ,  Randal W. Chance ,  Ward D. Parkinson

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L29/6659 ,  H01L21/823807

    摘要： An improved CMOS fabrication process which uses separate masking steps to pattern N-channel and P-channel transistor gates from a single layer of conductively-doped polycrystalline silicon (poly). The object of the improved process is to reduce the cost and improve the reliability and manufacturability of CMOS devices by dramatically reducing the number of photomasking steps required to fabricate transistors. By processing N-channel and P-channel devices separately, the number of photomasking steps required to fabricate complete CMOS circuitry in a single-polysilicon-layer or single-metal layer process can be reduced from eleven to eight. Starting with a substrate of P-type material, N-channel devices are formed first, with unetched poly left in the future P-channel regions until N-channel processing is complete. The improved CMOS process provides the following advantages over conventional process technology. Use of a masked high-energy punch-through implant for N-channel devices is not required; individual optimization of N-channel and P-channel transistors is made possible; a lightly-doped drain (LDD) design for both N-channel and P-channel transistors is readily implemented; source/drain-to-gate offset may be changed independently for N-channel and P-channel devices; and N-channel and P-channel transistors can be independently controlled and optimized for best LDD performance and reliability.

    摘要翻译： 一种改进的CMOS制造工艺，其使用单独的掩模步骤来从单层导电掺杂多晶硅（poly）中的N沟道和P沟道晶体管栅极图案化。 改进的过程的目的是通过显着减少制造晶体管所需的光掩模步骤的数量来降低成本并提高CMOS器件的可靠性和可制造性。 通过分别处理N沟道和P沟道器件，在单多晶硅层或单金属层工艺中制造完整的CMOS电路所需的光掩模步骤的数量可以从11减少到8个。 从P型材料的衬底开始，首先形成N沟道器件，在未来的P沟道区域中留下未蚀刻的聚合物，直到N沟道处理完成。 与传统工艺技术相比，改进的CMOS工艺提供了以下优点。 不需要对N沟道器件使用屏蔽的高能穿孔植入物; N通道和P沟道晶体管的单独优化成为可能; 容易实现用于N沟道和P沟道晶体管的轻掺杂漏极（LDD）设计; 源/漏 - 门偏移可以针对N沟道和P沟道器件独立地改变; 可以独立控制和优化N沟道和P沟道晶体管，以获得最佳的LDD性能和可靠性。

    Pull up circuit for sense lines in a semiconductor memory
    82.
    发明授权
    Pull up circuit for sense lines in a semiconductor memory 失效
    上拉电路用于半导体存储器中的感测线

    公开(公告)号：US4914631A

    公开(公告)日：1990-04-03

    申请号：US252585

    申请日：1988-09-30

    申请人： Gary M. Johnson ,  Zhitong Chen ,  Wen-Foo Chern ,  Ward D. Parkinson ,  Tyler A. Lowrey ,  Thomas M. Trent

    发明人： Gary M. Johnson ,  Zhitong Chen ,  Wen-Foo Chern ,  Ward D. Parkinson ,  Tyler A. Lowrey ,  Thomas M. Trent

    IPC分类号： G11C11/4094

    CPC分类号： G11C11/4094

    摘要： A memory array (e.g., DRAM) is provided with a potential maintenance circuit which provides sufficient current to maintain a high potential node of the memory array at a predetermined potential. The potential maintenance circuit is gated ON after receipt of a clock signal and gated OFF at the predetermined potential. This permits the high voltage node to be maintained, while reducing current requirements. The invention is particularly useful when used in conjunction with a circuit which rapidly pulls up the high node to a value of V.sub.CC -V.sub.T (where VT is a threshold voltage of a transistor).

    摘要翻译： 存储器阵列（例如，DRAM）设置有潜在的维护电路，其提供足够的电流以将存储器阵列的高电位节点保持在预定电位。 在接收到时钟信号并在预定电位门控OFF之后，潜在维护电路被选通。 这允许高压节点被维持，同时减少电流要求。 当与将快速将高节点上拉到VCC-VT（其中VT是晶体管的阈值电压）的电路结合使用时，本发明特别有用。

    Semiconductor ICF Target Processing
    83.
    发明申请
    Semiconductor ICF Target Processing 有权

    公开(公告)号：US20210358644A1

    公开(公告)日：2021-11-18

    申请号：US15930056

    申请日：2020-05-12

    申请人： Tyler A. Lowrey

    发明人： Tyler A. Lowrey

    IPC分类号： G21B1/19

    摘要： A method of manufacturing a semiconductor ICF target is described. On an n-type silicon wafer a plurality of hard mask layers are etched to a desired via pattern. Then isotropically etching hemispherical cavities, lithographically patterning the hard mask layers, conformally depositing ablator/drive material(s) and shell layer material(s), inserting hollow silicon dioxide fuel spheres in the hemisphere cavities, thermally bonding a mating wafer with matching hemisphere cavities and etching in ethylene diamine-pryrocatechol-water mixture to selectively remove n-type silicon and liberate the spherical targets.

    Memory array having floating gate semiconductor device
    84.
    发明授权
    Memory array having floating gate semiconductor device 失效
    具有浮置栅极半导体器件的存储器阵列

    公开(公告)号：US07956396B2

    公开(公告)日：2011-06-07

    申请号：US11933728

    申请日：2007-11-01

    申请人： Trung Tri Doan ,  Tyler A. Lowrey

    发明人： Trung Tri Doan ,  Tyler A. Lowrey

    IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42336 ,  H01L29/7881

    摘要： A method for forming a floating gate semiconductor device such as an electrically erasable programmable read only memory is provided. The device includes a silicon substrate having an electrically isolated active area. A gate oxide, as well as other components of a FET (e.g., source, drain) are formed in the active area. A self aligned floating gate is formed by depositing a conductive layer (e.g., polysilicon) into the recess and over the gate oxide. The conductive layer is then chemically mechanically planarized to an endpoint of the isolation layer so that all of the conductive layer except material in the recess and on the gate oxide is removed. Following formation of the floating gate an insulating layer is formed on the floating gate and a control gate is formed on the insulating layer.

    摘要翻译： 提供了一种用于形成诸如电可擦除可编程只读存储器的浮置栅极半导体器件的方法。 该器件包括具有电隔离的有源区的硅衬底。 栅极氧化物以及FET的其它部件（例如，源极，漏极）形成在有源区域中。 通过将导电层（例如多晶硅）沉积到栅极氧化物上而形成自对准浮栅。 然后将导电层化学机械平面化到隔离层的端点，使得去除凹部中和栅极氧化物上的材料以外的所有导电层。 在形成浮栅之后，在浮栅上形成绝缘层，在绝缘层上形成控制栅。

    Memory and access device and method therefor
    85.
    发明授权
    Memory and access device and method therefor 有权
    内存和访问设备及其方法

    公开(公告)号：US07906369B2

    公开(公告)日：2011-03-15

    申请号：US12538904

    申请日：2009-08-11

    申请人： Tyler A. Lowrey

    发明人： Tyler A. Lowrey

    IPC分类号： H01L21/06

    CPC分类号： H01L27/2427 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144 ,  H01L45/1675

    摘要： Briefly, in accordance with an embodiment of the invention, a memory and a method to manufacture the memory is provided. The memory may include a phase change material over a substrate. The memory may further include a switching material coupled to the phase change material, wherein the switching material comprises a chalcogen other than oxygen and wherein the switching material and the phase change material form portions of a vertical structure over the substrate.

    摘要翻译： 简而言之，根据本发明的实施例，提供了一种用于制造存储器的存储器和方法。 存储器可以包括在衬底上的相变材料。 存储器还可以包括耦合到相变材料的开关材料，其中开关材料包括除氧以外的硫族元素，并且其中开关材料和相变材料在衬底上形成垂直结构的部分。

    Memory cell arrays
    88.
    发明授权
    Memory cell arrays 失效
    存储单元阵列

    公开(公告)号：US07045834B2

    公开(公告)日：2006-05-16

    申请号：US10059727

    申请日：2002-01-29

    申请人： Luan Tran ,  D. Mark Duncan ,  Tyler A. Lowrey ,  Rob B. Kerr ,  Kris K. Brown

    发明人： Luan Tran ,  D. Mark Duncan ,  Tyler A. Lowrey ,  Rob B. Kerr ,  Kris K. Brown

    IPC分类号： H01L27/10 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

    CPC分类号： H01L27/10852 ,  H01L27/10808 ,  H01L27/10885

    摘要： A memory device includes memory cells, bit lines, active area lines running generally in parallel to the bit lines, and transistors formed in each active area line and electrically coupling memory cells to corresponding bit lines. Each bit line includes slanted portions that intersect a corresponding portion of an active area line at an angle. Contacts electrically coupling the bit line to portions of the active area line are formed in a region generally defined by the angled intersection of the bit line to the active area line. The memory cells can have an area of about 6F2, and the bit lines can be coupled to sense amplifiers in a folded bit line configuration. Each bit line includes a first level portion and a second level portion.

    摘要翻译： 存储器件包括存储器单元，位线，通常与位线平行地运行的有源区线以及在每个有源区域线中形成的晶体管，并将存储单元电耦合到相应的位线。 每个位线包括以一角度与有源区域线的相应部分相交的倾斜部分。 将位线电耦合到有源区域线的部分的触点形成在通常由位线到有源区域线的成角度的交叉点限定的区域中。 存储器单元可以具有约6F 2的面积，并且位线可以以折叠位线配置耦合到读出放大器。 每个位线包括第一电平部分和第二电平部分。