公开(公告)号：US10586735B2

公开(公告)日：2020-03-10

申请号：US15886717

申请日：2018-02-01

Applicant: United Microelectronics Corp.

Inventor： Kai-Kuen Chang ,  Shih-Yin Hsiao

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L27/092 ,  H01L29/78 ,  H01L21/8234

Abstract: A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.

公开(公告)号：US20190287860A1

公开(公告)日：2019-09-19

申请号：US16428651

申请日：2019-05-31

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Ching-Chung Yang ,  Kuan-Liang Liu

IPC: H01L21/8234 ,  H01L29/78 ,  H01L21/8249 ,  H01L29/49 ,  H01L27/02 ,  H01L29/06 ,  H01L29/423

Abstract: A transistor structure includes a source region and a drain region disposed in a substrate, extending along a first direction. A polysilicon layer is disposed over the substrate, extending along a second direction perpendicular to the first direction, wherein the polysilicon layer includes a first edge region, a channel region and a second edge region formed as a gate region between the source region and the drain region in a plane view. The polysilicon layer has at least a first opening pattern at the first edge region having a first portion overlapping with the gate region; and at least a second opening pattern at the second edge region having a second portion overlapping with the gate region.

公开(公告)号：US10411088B2

公开(公告)日：2019-09-10

申请号：US15951966

申请日：2018-04-12

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Shih-Chieh Pu ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/51 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/423 ,  H01L21/311

Abstract: A semiconductor device including a substrate and a shallow trench isolation (STI) structure is provided. The substrate has a first voltage area and a second voltage area. A top surface of the substrate in the second voltage area is higher than a top surface of the substrate in the first voltage area, and a trench is defined in the substrate in between the first and second voltage area. The STI structure is located in the substrate within the trench, wherein a first portion of the STI structure is located in the first voltage area, a second portion of the STI structure is located in the second voltage area, and a step height difference exist in between a bottom surface of the first portion of the STI structure in the first voltage area and a bottom surface of the second portion of the STI structure in the second voltage area.

公开(公告)号：US10373837B2

公开(公告)日：2019-08-06

申请号：US15705014

申请日：2017-09-14

Applicant: United Microelectronics Corp.

Inventor： Kun-Huang Yu ,  Shih-Yin Hsiao

IPC: H01L27/115 ,  H01L21/28 ,  H01L29/423 ,  H01L27/11536 ,  H01L27/11539

Abstract: Provided is a memory device including a first gate, a second gate and an inter-gate dielectric layer. The first gate is buried in a substrate. The second gate includes metal and is disposed on the substrate. The inter-gate dielectric layer is disposed between the first and second gates. The inter-gate dielectric layer comprises a high-k layer having a dielectric constant of greater than about 10.

公开(公告)号：US10297455B2

公开(公告)日：2019-05-21

申请号：US15292775

申请日：2016-10-13

Applicant: United Microelectronics Corp.

Inventor： Shih-Yin Hsiao ,  Shu-Wen Lin ,  Ke-Feng Lin ,  Hsin-Liang Liu ,  Chang-Lin Chen

IPC: H01L21/8234 ,  H01L21/28 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78

Abstract: A method for forming a gate oxide layer on a substrate is provided, in which a region of the substrate is defined out by a shallow trench isolation (STI) structure. An oxide layer covers over the substrate and a mask layer with an opening to expose oxide layer corresponding to the region with an interface edge of the STI structure. The method includes forming a silicon spacer on a sidewall of the opening. A cleaning process is performed through the opening to expose the substrate at the region. An oxidation process is performed on the substrate at the region to form the gate oxide layer, wherein the silicon spacer is also oxidized to merge to an edge of the gate oxide layer.

公开(公告)号：US20190006528A1

公开(公告)日：2019-01-03

申请号：US15660982

申请日：2017-07-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kai-Kuen Chang ,  Ching-Chung Yang

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/40

Abstract: A high voltage device includes a semiconductor substrate, an ion well, a Schottky diode in the ion well, an isolation structure in the ion well surrounding the Schottky diode, and an assistant gate surrounding the Schottky diode. The assistant gate is disposed only on the isolation structure and is not in direct contact with the ion well.

公开(公告)号：US20180197742A1

公开(公告)日：2018-07-12

申请号：US15402970

申请日：2017-01-10

Applicant: United Microelectronics Corp.

Inventor： Kai-Kuen Chang ,  Shih-Yin Hsiao

IPC: H01L21/265 ,  H01L21/266

CPC classification number: H01L21/26513 ,  H01L21/26586 ,  H01L21/266 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/1095

Abstract: A doping method for a semiconductor device including the following steps is provided. A substrate is provided. The substrate has a channel region. The channel region includes a first edge region, a second edge region and a center region in a channel width direction substantially perpendicular to a channel length direction, and the center region is located between the first edge region and the second edge region. A first doping process is performed on the first edge region, the second edge region and the center region by using a first conductive type dopant. A second doping process is performed on the center region by using a second conductive type dopant.

公开(公告)号：US20180102408A1

公开(公告)日：2018-04-12

申请号：US15287535

申请日：2016-10-06

Applicant: United Microelectronics Corp.

Inventor： Chang-Po Hsiung ,  Ping-Hung Chiang ,  Shih-Chieh Pu ,  Chia-Lin Wang ,  Nien-Chung Li ,  Wen-Fang Lee ,  Shih-Yin Hsiao ,  Chih-Chung Wang

IPC: H01L29/06 ,  H01L29/51 ,  H01L21/762 ,  H01L21/311 ,  H01L27/088

CPC classification number: H01L29/0649 ,  H01L21/31111 ,  H01L21/7621 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/088 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/517

Abstract: A method of forming a semiconductor device is provided including the following steps. A substrate having a first voltage area and a second voltage area is provided. A first oxide layer is formed in the first voltage area. The first oxide layer is removed to form a recess in the first voltage area. A shallow trench isolation (STI) structure is formed in the substrate, wherein a first portion of the STI structure is located in the first voltage area and a second portion of the STI structure is located in the second voltage area, a top surface of the STI structure is higher than the top surface of the substrate, and a bottom surface of the first portion of the STI structure in the first voltage area is lower than a bottom surface of the second portion of the STI structure in the second voltage area.

公开(公告)号：US09922881B2

公开(公告)日：2018-03-20

申请号：US14993623

申请日：2016-01-12

Applicant: United Microelectronics Corp.

Inventor： Kai-Kuen Chang ,  Shih-Yin Hsiao

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/423 ,  H01L29/08 ,  H01L27/092

CPC classification number: H01L21/823462 ,  H01L21/823418 ,  H01L21/823437 ,  H01L27/088 ,  H01L27/0922 ,  H01L29/0847 ,  H01L29/42364 ,  H01L29/7836

Abstract: A method for fabricating a semiconductor device structure is shown. A gate dielectric layer is formed on a substrate. A portion of the gate dielectric layer, which is located on a part of the substrate in which an S/D region is to be formed, is removed. A gate electrode is formed on the remaining gate dielectric layer. A spacer is formed on the sidewall of the gate electrode and the sidewall of the gate dielectric layer. The S/D region is then formed in the part of the substrate beside the spacer.

公开(公告)号：US20180047809A1

公开(公告)日：2018-02-15

申请号：US15234432

申请日：2016-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Kai-Kuen Chang

IPC: H01L29/08 ,  H01L21/266 ,  H01L29/732 ,  H01L29/10

CPC classification number: H01L29/1004 ,  H01L29/0653 ,  H01L29/0813 ,  H01L29/66272 ,  H01L29/732

Abstract: A bipolar junction transistor (BJT) device includes a semiconductor substrate, a first doping region with a first conductivity, a second doping region with a second conductivity, a third doping region with the first conductivity, at least one stacked block and a conductive contact. The first doping region is formed in the semiconductor substrate. The second doping region is formed in the first doping region. The at least one stacked block is formed on and insulated from the second doping region. The third doping region is formed in the second doping region and disposed adjacent to the at least one stacked block. The conductive contact electrically connects the at least one stacked block with the third doping region.