公开(公告)号：US6029011A

公开(公告)日：2000-02-22

申请号：US159708

申请日：1998-09-24

申请人： Yoichi Sato

发明人： Yoichi Sato

IPC分类号： G03B7/16 ,  G03B15/05

CPC分类号： G03B7/16

摘要： A control device for a flash device used for a camera, or a camera adapted to use a flash device, includes an object luminance detecting sensor part for making preliminary light emission before exposure and measuring object luminance obtained during the preliminary light emission, an aperture value determining circuit for determining a full-open aperture value of a photo-taking lens used for the camera, a deciding circuit for deciding an amount of light emission to be made by the flash device during exposure by the camera, in accordance with a detection result of the object luminance detecting sensor part and a determination result of the aperture value determining circuit, and a restraining circuit for finding whether the camera is in such a state as to have the full-open aperture value correctly determined by the aperture value determining circuit and, if the camera is found to be not in such a state as to have the full-open aperture value correctly determined by the aperture value determining circuit, restraining light-emission control of the flash device based on a decision of the deciding circuit from being performed.

摘要翻译： 用于相机的闪光灯装置的控制装置或适用于闪光装置的照相机的照相机的控制装置包括用于在曝光之前进行初步发光并且测量在初步发光期间获得的物体亮度的物体亮度检测传感器部分， 确定电路，用于确定用于照相机的摄影镜头的全开孔径值;判定电路，用于根据检测结果确定由照相机曝光期间由闪光灯装置产生的发光量 对象亮度检测传感器部分的确定结果和光圈值确定电路的确定结果;以及抑制电路，用于确定相机是否处于由光圈值确定电路正确确定的全开孔径值的状态;以及 如果发现照相机不处于由光圈值d正确确定的全开孔径值的状态 终止电路，基于决定电路的判定来抑制闪光灯装置的发光控制。

公开(公告)号：US5729173A

公开(公告)日：1998-03-17

申请号：US668374

申请日：1996-06-18

申请人： Yoichi Sato

发明人： Yoichi Sato

IPC分类号： H04L27/38

CPC分类号： H04L27/3872

摘要： A quadrature amplitude modulation demodulator for receiving a quadrature amplitude modulated signal having a suppressed pilot signal. In the demodulator, a receiver unit converts received quadrature amplitude modulated signal into a frequency converted signal and a signal at a phase 90 degrees shifted from this frequency converted signal. A synchronous detector unit performs synchronous detection on the signals outputted by the receiver unit by detecting a frequency difference between a carrier of the frequency converted signal and a reference signal. Then, a phase detector unit performs phase detection on the synchronous detected signals by detecting a phase difference included in the synchronous detected signals. A detector unit detects transmitted data from the phase detected signal. The present invention also provides a demodulator which can accurately detect transmitted symbols from a received quadrature amplitude modulated signal having a suppressed carrier component, and enters into a fully receivable state in a reduced time from the start of reception, and a receiver which determines optimal sampling timing and an optimal amplification factor for a received signal by independent control schemes without mutual interference.

摘要翻译： 一种用于接收具有抑制的导频信号的正交幅度调制信号的正交幅度调制解调器。 在解调器中，接收机单元将接收到的正交幅度调制信号转换为频率转换信号和从该频率转换信号偏移90度的相位的信号。 同步检测器单元通过检测频率转换信号的载波与参考信号之间的频率差来对接收器单元输出的信号进行同步检测。 然后，相位检测器单元通过检测包含在同步检测信号中的相位差来对同步检测信号进行相位检测。 检测器单元从相位检测信号检测发送的数据。 本发明还提供一种解调器，其可以从接收到的具有抑制的载波分量的正交幅度调制信号中精确地检测发射符号，并且在从接收开始的减少时间内进入完全可接收状态，以及确定最佳采样的接收机 定时和通过独立控制方案的接收信号的最佳放大系数，而没有相互干扰。

公开(公告)号：US5317537A

公开(公告)日：1994-05-31

申请号：US888493

申请日：1992-05-27

申请人： Satoshi Shinagawa ,  Yoichi Sato ,  Masami Hasegawa ,  Yasushi Shimono ,  Masayuki Miyasaka ,  Takatoshi Tamura ,  Yoshio Iioka

发明人： Satoshi Shinagawa ,  Yoichi Sato ,  Masami Hasegawa ,  Yasushi Shimono ,  Masayuki Miyasaka ,  Takatoshi Tamura ,  Yoshio Iioka

IPC分类号： G11C11/41 ,  G11C7/14 ,  G11C8/16 ,  H04Q3/52 ,  H04Q11/04 ,  G11C13/00

CPC分类号： G11C7/14 ,  G11C8/16

摘要： A multi-port memory device has a memory cell array including one or more memory blocks each of which has a plurality of memory cells arranged in rows and columns, and a plurality of dummy cells, with one dummy cell being provided for each row of memory cells in each of the memory blocks so that the dummy cells are connected with associated ones of the word lines extending in the row direction. The dummy cells are further connected with dummy cell bit lines extending in the column direction. Sense amplifiers are connected to receive outputs of those memory cells in the memory cell array which are selected in a memory cell selection operation and outputs of those dummy cells among the plurality of dummy cells which are selected in the memory cell selection operation for amplifying differences between the selected memory cell outputs and the selected dummy cell outputs. Precharging and shielding arrangements are also provided for improved operation.

摘要翻译： 多端口存储器件具有包括一个或多个存储器块的存储单元阵列，每个存储块具有以行和列排列的多个存储器单元，以及多个虚设单元，每个存储器行提供一个虚拟单元 每个存储器块中的单元，使得虚设单元与在行方向上延伸的字线相关联地连接。 虚拟单元进一步与在列方向上延伸的虚拟单元位线连接。 连接感测放大器以接收在存储单元选择操作中选择的存储单元阵列中的这些存储单元的输出，并且在存储单元选择操作中选择的多个虚设单元中的这些虚设单元的输出， 所选择的存储单元输出和所选择的虚拟单元输出。 还提供了预充电和屏蔽装置，以改善操作。

公开(公告)号：US5065363A

公开(公告)日：1991-11-12

申请号：US637809

申请日：1991-01-07

申请人： Yoichi Sato ,  Masao Mizukami

发明人： Yoichi Sato ,  Masao Mizukami

IPC分类号： G11C11/412 ,  G11C11/41 ,  G11C11/413 ,  G11C11/419 ,  H01L21/8244 ,  H01L27/11

CPC分类号： G11C11/41 ,  G11C11/413

摘要： Each memory cell of the memory array has a latch circuit, such as a pair of cross-connected CMOS inverters, for storing information, a first switch MOSFET whose gate is connected with a word line, and a second switch MOSFET which is connected in series with the first switch MOSFET and the gate of which is connected with the output terminal of the latch circuit. The first and second switch MOSFETs are coupled between the data line and a terminal supplied with a first power source voltage level, such as reference ground potential. Such memory cells are disposed at intersections of a plurality of data lines and a plurality of word lines. One of the plurality of data lines is connected with a common data line through a column switch which is alternatively brought into an ON state. Prior to a reading operation, the data lines are prechanged to the first power-source voltage level, or ground potential, and the common data line is precharged to a second power-source voltage level, such as the supply voltage of the memory. The memory array is implemented in a semiconductor storage device, such as a static RAM, which is characterized as operating either as a one-port or two-port system and wherein it, furthermore, employs a write amplifier circuit arrangement and a sense amplifier arrangement, such as of the single-ended differential type, wherein the write and sense amplifier arrangements can be disposed either on separate common data lines or on a single common data line.

摘要翻译： 存储器阵列的每个存储单元具有用于存储信息的锁存电路，例如一对交叉连接的CMOS反相器，栅极与字线连接的第一开关MOSFET，以及串联连接的第二开关MOSFET 其中第一开关MOSFET和其栅极与锁存电路的输出端相连。 第一和第二开关MOSFET耦合在数据线和提供有第一电源电压电平（例如参考地电位）的端子之间。 这样的存储单元设置在多条数据线和多条字线的交点处。 多个数据线中的一个通过列开关与公共数据线连接，该列开关被替代地进入ON状态。 在读取操作之前，数据线被改变为第一电源电压电平或地电位，并且公共数据线被预充电到诸如存储器的电源电压的第二电源电压电平。 存储器阵列实现在诸如静态RAM的半导体存储设备中，其被表征为作为单端口或双端口系统操作，并且其中其还采用写放大器电路布置和读出放大器布置 ，例如单端差分型，其中写入和读出放大器布置可以设置在单独的公共数据线上或在单个公共数据线上。

公开(公告)号：US5053652A

公开(公告)日：1991-10-01

申请号：US637591

申请日：1991-01-04

申请人： Yoichi Sato ,  Masao Mizukami ,  Toshiyuki Ookuma

发明人： Yoichi Sato ,  Masao Mizukami ,  Toshiyuki Ookuma

IPC分类号： G11C7/06 ,  G11C8/16

CPC分类号： G11C7/062 ,  G11C8/16

摘要： A semiconductor memory device has a sense amplifier which is constructed with a level shift circuit having an input which senses the change in a data line from an initial precharged level to a level near the vicinity of the supply voltage level which corresponds to data reading amounts from a memory cell during the reading mode of operation of the memory. The level shift circuit, in response to a memory cell reading signals, provides a level shifted outpout to the input terminal of a differential sense amplifier circuit, the level shifted output being in the vicinity of the operating point of the differential sense amplifier circuit. The level shift circuit includes a current amplifier having an output terminal that is formed with a series connecting node of a current amplifying transistor and a current source.

摘要翻译： 半导体存储器件具有读出放大器，该读出放大器由具有输入的电平移位电路构成，该输入检测从初始预充电电平到数据线附近的电平变化附近的数据线对应于来自 在存储器的操作的读取模式期间的存储器单元。 电平移位电路响应于存储单元读取信号，向差分读出放大器电路的输入端提供电平偏移输出，电平移位输出位于差分读出放大器电路的工作点附近。 电平移位电路包括具有由电流放大晶体管和电流源的串联连接节点形成的输出端子的电流放大器。

公开(公告)号：US4810838A

公开(公告)日：1989-03-07

申请号：US70912

申请日：1987-07-08

申请人： Kazuo Ichinokawa ,  Yoichi Sato ,  Tadashi Otsuka

发明人： Kazuo Ichinokawa ,  Yoichi Sato ,  Tadashi Otsuka

IPC分类号： G01B7/00 ,  G06F3/033 ,  G06F3/046 ,  G08C21/00

CPC分类号： G06F3/046

摘要： A frequency coupling position coordinates determination apparatus includes sheet means on which N (positive integer) one-turn coils for detecting a magnetic force and M (less than N) signal lines to which at least one predetermined one-turn coil of the N one-turn coils is connected are arranged, and detecting means for detecting the amplitudes of currents respectively flowing through the M signal lines.

摘要翻译： 频率耦合位置坐标确定装置包括薄片装置，N个（正整数）单匝线圈用于检测磁力，M（小于N）个信号线，N个单向线圈的至少一个预定单匝线圈， 布置有转向线圈，以及检测装置，用于检测分别流过M条信号线的电流的幅度。

公开(公告)号：US4688530A

公开(公告)日：1987-08-25

申请号：US822072

申请日：1986-01-24

申请人： Masao Nishikawa ,  Takashi Aoki ,  Yoichi Sato ,  Yukihiro Fukuda

发明人： Masao Nishikawa ,  Takashi Aoki ,  Yoichi Sato ,  Yukihiro Fukuda

IPC分类号： B60K25/02 ,  B60H1/32 ,  B60K17/28 ,  B60K25/00 ,  F02D9/02 ,  F16H59/22 ,  F16H59/44 ,  F16H59/50 ,  F16H61/20 ,  F02B77/00

CPC分类号： B60K25/00 ,  F16H61/20 ,  F16H59/22 ,  F16H59/44 ,  F16H59/50

摘要： A control system for an accessory of an automobile includes an engine output detector for detecting the output of the engine of the automobile, a gear transmissioon coupled to the engine and responsive to detection of an idling condition of the automboile for selecting a neutral gear position, an accessory such as an air conditioner compressor drivable by the engine, a clutch disposed between the accessory and the engine for applying and cutting off the output of the engine to the accessory, a speed sensor for detecting the speed of travel of the automobile, a control circuit for comparing an actual running condition of the automobile with a prescribed running condition in which the output of the engine and the speed of the automobile are lower than respective prescribed levels, and for inhibiting operation of the accessory by disconnecting the clutch when the automobile is under the prescribed running condition.

摘要翻译： 用于汽车附件的控制系统包括用于检测汽车的发动机的输出的发动机输出检测器，耦合到发动机的齿轮传动装置，并且响应于检测到用于选择空档档位的自动汽缸的空转状态， 诸如由发动机驱动的空调压缩机的附件，设置在附件和发动机之间的离合器，用于将发动机的输出施加和切断到附件，用于检测汽车行驶速度的速度传感器， 控制电路，用于将汽车的实际运行状态与发动机的输出和汽车的速度低于规定水平的规定行驶条件进行比较，并且当汽车 处于规定的运行状态。

公开(公告)号：US4589537A

公开(公告)日：1986-05-20

申请号：US551739

申请日：1983-11-14

申请人： Masao Nishikawa ,  Yoshimi Sakurai ,  Takashi Aoki ,  Yoichi Sato

发明人： Masao Nishikawa ,  Yoshimi Sakurai ,  Takashi Aoki ,  Yoichi Sato

IPC分类号： F16H45/02 ,  F16H59/22 ,  F16H61/02 ,  F16H61/14 ,  B60K41/28

CPC分类号： F16H45/02 ,  F16H61/143 ,  F16H2041/246 ,  F16H2061/026 ,  F16H2061/145 ,  F16H59/22 ,  Y10T477/6352 ,  Y10T477/6425 ,  Y10T477/6939

摘要： In an automatic transmission comprising a fluid type torque converter having an input member including a pump vane wheel and an output member including a turbine vane wheel, and an auxiliary transmission having one or plural stages of gear trains through which the torque of said output member is transmitted to driving wheels, a lock-up control device for a torque converter in an automatic transmission for vehicle comprising a hydraulic direct coupling clutch having a slip characteristic provided between the input and output members of the torque converter and capable of mechanically coupling said both members and a modulator valve disposed in an oil passage for connecting an oil pressure cylinder of said direct coupling clutch with an oil pressure source, said modulator valve being composed of a valve body for opening and closing said oil passage, a spring for biasing said valve body in a valve-opening direction, a first oil pressure chamber for introducing pilot oil pressure for biasing said valve body in a valve-closing direction from an input port side of said modulator valve, and a second pilot oil pressure chamber for introducing pilot oil pressure for biasing said valve body in the valve-opening direction, wherein an output side of a device for generating oil pressure proportional to vehicle speed for releasing oil pressure which is changed proportional to the vehicle speed is connected through a throttle to said second pilot oil pressure chamber and a valve device for detecting the idle state of an engine throttle valve to release said second pilot oil pressure chamber to atmosphere is connected to said second pilot oil pressure chamber.

摘要翻译： 一种自动变速器，包括具有输入构件的流体式变矩器，所述输入构件包括泵叶轮和包括涡轮叶轮的输出构件，以及具有一级或多级齿轮系的辅助变速器，所述输出构件的扭矩通过该辅助变速器 传动到驱动轮，用于车辆自动变速器中的变矩器的锁定控制装置，包括具有设置在变矩器的输入和输出构件之间的滑动特性的液压直接联轴器离合器，并且能够机械地联接所述两个构件 以及调节阀，设置在油路中，用于将所述直接联接离合器的油压缸与油压源连接，所述调节阀由用于打开和关闭所述油通道的阀体组成，用于偏压所述阀体的弹簧 在阀打开方向上，用于引入用于偏压的先导油压的第一油压室 从所述调节阀的输入口侧沿阀关闭方向截取所述阀体;以及第二先导油压室，用于引入用于沿所述阀打开方向偏压所述阀体的先导油压，其中， 用于产生与车速成比例的油压以释放与车速成比例的油压的装置通过节气门连接到所述第二先导油压室和用于检测发动机节气门的怠速状态以释放所述第二先导油压室的阀装置 第二先导油压室连接到所述第二先导油压室。

公开(公告)号：US08305789B2

公开(公告)日：2012-11-06

申请号：US12977243

申请日：2010-12-23

申请人： Kanji Otsuka ,  Tsuneo Ito ,  Yoichi Sato ,  Masahiro Yoshida ,  Shigeru Yamamoto ,  Takeshi Koyama ,  Yuko Tanba ,  Yutaka Akiyama

发明人： Kanji Otsuka ,  Tsuneo Ito ,  Yoichi Sato ,  Masahiro Yoshida ,  Shigeru Yamamoto ,  Takeshi Koyama ,  Yuko Tanba ,  Yutaka Akiyama

IPC分类号： G11C5/06

CPC分类号： G06F13/4022 ,  G11C5/02 ,  G11C7/1006 ,  G11C2213/71

摘要： A bandwidth bottleneck occurs because a crossbar switch is used to cope with an increase in scale. A memory/logic conjugate system according to the present invention, a plurality of cluster memory chips each including a plurality of cluster memories 20 including basic cells 10 arranged in a cluster, the basic cell 10 including a memory circuit, and a controller chip that controls the plurality of cluster memories are three-dimensionally stacked, the plurality of cluster memories 20 located along the stacking direction of the plurality of cluster memory chips and the controller chip are electrically coupled to the controller chip via a multibus 11 including a through-via, an arbitrary one of the basic cells 10 is directly accessed through the multibus 11 from the controller chip so that truth value data is written therein, and whereby the arbitrary basic cell 10 is switched to a logic circuit as conjugate.

摘要翻译： 发生带宽瓶颈是因为使用横杠开关来应对规模的增加。 根据本发明的存储器/逻辑共轭系统，多个集群存储器芯片，每个集群存储器芯片包括多个集群存储器20，集群存储器20包括布置在集群中的基本单元10，基本单元10包括存储器电路，以及控制芯片， 多个集群存储器是三维堆叠的，沿着多个集群存储器芯片的堆叠方向定位的多个集群存储器20和控制器芯片经由包括通孔的多通道11电耦合到控制器芯片， 基本单元10中的任意一个基本单元10通过多轴11从控制器芯片直接访问，从而将真值数据写入其中，并且由此将任意基本单元10切换到逻辑电路作为共轭。

公开(公告)号：US08186487B2

公开(公告)日：2012-05-29

申请号：US12699352

申请日：2010-02-03

申请人： Yasutaka Miura ,  Yoichi Sato ,  Masayuki Sugita ,  Yoshinori Yamanoi ,  Hitoshi Ohi ,  Atsushi Takano ,  Nobuteru Fujii

发明人： Yasutaka Miura ,  Yoichi Sato ,  Masayuki Sugita ,  Yoshinori Yamanoi ,  Hitoshi Ohi ,  Atsushi Takano ,  Nobuteru Fujii

IPC分类号： F16D65/14

CPC分类号： F16D65/18 ,  F16D2121/02 ,  F16D2121/14 ,  F16D2123/00 ,  F16D2125/60

摘要： A vehicle disc brake device for preventing snow, ice, and mud from adhering to a caliper includes a body-anchoring part provided in a cylinder of a caliper, the body-anchoring part for securing a wire guide used to support a brake wire. The body-anchoring part has a first surface oriented along the longitudinal direction of the brake wire, and a second surface located on the side opposite the first surface. A wire-guide-anchoring part is secured to the second surface. The first surface is a flat, inclined surface.

摘要翻译： 用于防止雪，冰和泥粘附到卡钳的车辆盘式制动装置包括设置在卡钳的气缸中的主体锚固部，用于固定用于支撑制动线的线引导件的车身锚固部。 身体锚定部具有沿着制动线的纵向取向的第一表面和位于与第一表面相对的一侧的第二表面。 线导向件固定在第二表面上。 第一个表面是平坦的，倾斜的表面。