摘要:
A differential type MOS transmission circuit includes a signal driving circuit and a signal receiving circuit to realize high speed transmission for a short distance transmission between different LSIs, etc. A pair of transmission lines between the signal driving circuit and the signal receiving circuit are driven by a pair of drivers in the signal driving circuit so as to take either one of three states, i.e. one state where both of the lines are in a precharged states and two states where either one of the lines is in a discharged state. A signal driving circuit includes signal generating circuits generating variations in control signals varying pulse-like in response to rise and fall of an input signal to thereby obtain the discharge state. The signal receiving circuit generates an output signal depending on the state of the transmission lines and is constructed of a Schmitt trigger circuit with a hysteresis characteristic, for which an input threshold voltage for output logical values has a level smaller than a potential difference between the precharged level and the discharged level.
摘要:
One paired wiring traveling in parallel to a transmission path of a signal and a transmission path of reference voltage is used, and a terminal end resistor matched with the characteristic impedance is installed, and in a receiving circuit connected thereto, a differential input circuit with offset set to about 1/2 of the terminal end voltage is used, and an output circuit of open drain is used in a transmitting circuit. A high-speed information processing section using such a bus circuit and a low-speed information processing section using a conventional low-speed bus are mutually connected through an interface circuit to construct the system hierarchically.
摘要:
A signal transmission system provides stable, fast, long-range transmission. During transmission, a short-width pulse is synchronized with rising and falling edges of a transmission pulse signal. A ternary output signal in a differential shape is produced on the basis of the pulse, and an output signal is transmitted through series resistors via a pair of transmitting wirings. During reception, a reception terminal is provided with terminal resistors corresponding to a characteristic impedance of the transmitting wirings. A signal having passed through one of the transmitting wirings is detected with reference to a signal having passed through the other transmitting wiring. A signal having passed through the other transmitting wiring is detected with reference to the signal having passed through the one transmitting wiring. Additionally, the original pulse signal is restored and reproduced on the basis of the detected signals. The signals to be transmitted through the paired transmitting wirings are bipolar pulses or differential pulses which are generated only at the rising and falling times of the pulse signal to be transmitted. The pulses are given a complementary transmission waveform having a small amplitude divided by the series resistors at the transmission side and the terminal resistors at the reception side. In consideration of the above, and since the signals containing no-DC component can be transmitted, the charging and discharging phenomena of the inter-line capacities and the DC shift can be eliminated to accomplish long-range transmissions at a high speed.
摘要:
Each memory cell of the memory array has a latch circuit, such as a pair of cross-connected CMOS inverters, for storing information, a first switch MOSFET whose gate is connected with a word line, and a second switch MOSFET which is connected in series with the first switch MOSFET and the gate of which is connected with the output terminal of the latch circuit. The first and second switch MOSFETs are coupled between the data line and a terminal supplied with a first power source voltage level, such as reference ground potential. Such memory cells are disposed at intersections of a plurality of data lines and a plurality of word lines. One of the plurality of data lines is connected with a common data line through a column switch which is alternatively brought into an ON state. Prior to a reading operation, the data lines are prechanged to the first power-source voltage level, or ground potential, and the common data line is precharged to a second power-source voltage level, such as the supply voltage of the memory. The memory array is implemented in a semiconductor storage device, such as a static RAM, which is characterized as operating either as a one-port or two-port system and wherein it, furthermore, employs a write amplifier circuit arrangement and a sense amplifier arrangement, such as of the single-ended differential type, wherein the write and sense amplifier arrangements can be disposed either on separate common data lines or on a single common data line.
摘要:
A semiconductor memory device has a sense amplifier which is constructed with a level shift circuit having an input which senses the change in a data line from an initial precharged level to a level near the vicinity of the supply voltage level which corresponds to data reading amounts from a memory cell during the reading mode of operation of the memory. The level shift circuit, in response to a memory cell reading signals, provides a level shifted outpout to the input terminal of a differential sense amplifier circuit, the level shifted output being in the vicinity of the operating point of the differential sense amplifier circuit. The level shift circuit includes a current amplifier having an output terminal that is formed with a series connecting node of a current amplifying transistor and a current source.
摘要:
A variable displacement compressor comprises a housing forming a crank chamber, a shaft, expansible chambers including pistons, a swash plate connected to the shaft so as to be smoothly changeable in inclination against the shaft and driven to rotate, a wobble plate rotatable on the swash plate, a rotation preventing mechanism including a shoe member slidable in an axial direction, and a pressure control valve which is provided in a refrigerant passage from a suction port of the compressor to the expansible chamber to control the pressure of refrigerant to be sucked responsive to the suction pressure and both to the suction pressure and to the discharge pressure when the discharge pressure is high. The refrigerant passage has a sharply bent portion for separating lubrication oil from a refrigerant flowing therein and communicates with the crank chamber to discharge blow-by gas therefrom.
摘要:
A signal receiving circuit comprising a first P-channel MOSFET amplifier and a first N-channel MOSFET amplifier having gates supplied with positive signals from a pair of signal transmission lines; and a second P-channel MOSFET amplifier and a second N-channel MOSFET amplifier having gates supplied with negative signals from said pair of signal transmission lines; wherein a first output signal is formed by so adjusting the gains of the first P-channel MOSFET amplifier and of the second N-channel MOSFET amplifier that the resultant signals have an intermediate amplitude between the operation voltages, and a second output signal is formed by so adjusting the gains of the second P-channel MOSFET amplifier and of the first N-channel MOSFET amplifier that the resultant signals have an intermediate amplitude between the operation voltages. This makes it possible to receive various small signals lying over a wide range even by using a sense amplifier which has only a fixed operation range in the signal receiving circuit as well as to constitute a novel and optimum system by combining semiconductor integrated circuit devices having different low-amplitude interfaces.
摘要:
Write column selection MOSFETs of memory cells MC are coupled with, for example, the earth potential of the circuit. Write column selection signals supplied to these MOSFETs are formed selectively according to the column selection address signal and the write data. Thereby the write column selection MOSFETs of the memory cells MC function as a substantial write means. That is, the write column selection signal lines are used as the data lines at the same time.
摘要:
A signal transmission circuit in which a signal is converted into two complementary signals which are outputted from a signal transmission circuit via series resistors. The amplitude of each of the complimentary signals is reduced by the series resistors and terminating resistors provided on a signal receiving side. The signal receiving side shifts the level of the signals which it inputs. The level shifted signals are amplified by a high-input impedance differential amplifying circuit.
摘要:
A moving vane type compressor has a cylinder which is made of a sintered material having a density of 6.6 to 7.6 and a composition consisting essentially of 0.6 to 0.8% of carbon, 1 to 2% of copper and the balance substantially iron. The cylinder is encased by a hermetic casing therebetween a high pressure chamber into which a refrigerant compressed by the compressor is discharged. Lubricating oil separated from the discharged refrigerant within the high pressure chamber and the lubricating oil suspended in the form of a mist by the refrigerant attach to the outer peripheral surface of the wall of the cylinder made of the sintered material. The oil attaching to the outer peripheral surface of the cylinder is forced by the refrigerant pressure acting thereon into the pores of the sintered material such as to block these pores, thus preventing the compressed gas in the cylinder from leaking outside through the pores.