公开(公告)号：US5892247A

公开(公告)日：1999-04-06

申请号：US546757

申请日：1995-10-23

申请人： Yukihito Oowaki ,  Mitsuhiro Noguchi ,  Tohru Maruyama

发明人： Yukihito Oowaki ,  Mitsuhiro Noguchi ,  Tohru Maruyama

IPC分类号： H01L21/18 ,  H01L21/285 ,  H01L21/335 ,  H01L29/423 ,  H01L29/66 ,  H01L29/76 ,  H01L29/778 ,  H01L29/788 ,  H01L31/0328

CPC分类号： B82Y10/00 ,  H01L21/28587 ,  H01L29/4232 ,  H01L29/66075 ,  H01L29/66462 ,  H01L29/66469 ,  H01L29/66977 ,  H01L29/7606 ,  H01L29/7613 ,  H01L29/7787 ,  H01L29/7883

摘要： The semiconductor device comprises a substrate, a first conductive layer formed on the substrate with a first insulating layer inserted therebetween, thereby to constitute a first gate electrode, a second conductive layer selectively formed on the first gate electrode with a second insulating layer inserted therebetween, and a third conductive layer formed on the first and second conductive layer, thereby to constitute first and second electrodes respectively connected to the first and second conductive layers.

摘要翻译： 半导体器件包括衬底，形成在衬底上的第一绝缘层的第一导电层，从而构成第一栅电极，第二导电层选择性地形成在第一栅电极上，第二绝缘层插入其间， 以及形成在第一和第二导电层上的第三导电层，从而构成分别连接到第一和第二导电层的第一和第二电极。

公开(公告)号：US5717625A

公开(公告)日：1998-02-10

申请号：US784963

申请日：1997-01-16

申请人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Shigeyoshi Watanabe ,  Ken-ichi Maeda ,  Mitsuo Saito ,  Masako Yoshida ,  Ryo Fukuda ,  Shinichiro Shiratake

发明人： Takehiro Hasegawa ,  Yukihito Oowaki ,  Shigeyoshi Watanabe ,  Ken-ichi Maeda ,  Mitsuo Saito ,  Masako Yoshida ,  Ryo Fukuda ,  Shinichiro Shiratake

IPC分类号： G11C8/08 ,  G11C11/404 ,  G11C15/00

CPC分类号： G11C8/08 ,  G11C11/4045

摘要： In a semiconductor memory device wherein a plurality of memory cell units formed by connecting a plurality of memory cells in series are provided and each of the memory cell units is connected to a bit line, the semiconductor memory device comprises control circuit for directly reading data of a register cell during a reading operation when the previous row address designates the same memory cell as the present row address, and a data changing controlling circuit for changing data of an arbitrary memory cell of the memory cell unit to data of the memory cell closest to the bit line contact in the memory cell unit, and a row decoder for corresponding row addresses which select the memory of memory cell units, to the upper addresses than the parts of the row addresses which select a memory unit among the memory cell units.

摘要翻译： 在其中提供通过串联连接多个存储单元而形成的多个存储单元单元的半导体存储器件中，并且每个存储单元单元连接到位线，该半导体存储器件包括用于直接读取数据的数据的控制电路 当前一行地址指定与当前行地址相同的存储单元时，读取操作期间的寄存器单元，以及数据改变控制电路，用于将存储单元单元的任意存储单元的数据改变为最靠近的存储单元的数据 存储单元单元中的位线接触，以及用于选择存储单元单元的存储器的相应行地址的行解码器，比存储单元单元中选择存储单元的行地址的部分高。

公开(公告)号：US5684746A

公开(公告)日：1997-11-04

申请号：US567688

申请日：1995-12-05

申请人： Yukihito Oowaki ,  Ryo Fukuda

发明人： Yukihito Oowaki ,  Ryo Fukuda

IPC分类号： G11C11/413 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24 ,  H01L21/82 ,  H01L27/10 ,  G11C7/00

CPC分类号： G11C29/76 ,  G11C29/24

摘要： A semiconductor memory device including a memory cell array having memory cells arranged in XY directions, means for storing at least X addresses of failure bit memory cells among memory cells defined by an X address and a Y address in the memory cell array, and address means for generating an address Xe+m (m=positive or negative integer), serving as an internal address, when X address Xe corresponding to the failure bit address is inputted from an external section.

摘要翻译： 一种半导体存储器件，包括具有以XY方向布置的存储单元的存储单元阵列，用于在存储单元阵列中由X地址和Y地址定义的存储单元中存储故障位存储单元的至少X个地址的装置，以及地址单元 用于当从外部输入与故障位地址对应的X地址Xe时，产生用作内部地址的地址Xe + m（m =正或负整数）。

公开(公告)号：US4825268A

公开(公告)日：1989-04-25

申请号：US213435

申请日：1988-06-27

申请人： Yukihito Oowaki

发明人： Yukihito Oowaki

IPC分类号： H01L27/10 ,  G11C5/00 ,  G11C11/404 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  H01L27/02

CPC分类号： G11C5/005 ,  G11C11/404 ,  Y10S257/929

摘要： A semiconductor memory device comprises a plurality of one-bit memory cells each having a MOS transistor and a MOS capacitor and arranged two-dimensionally. Of the memory cells along the column direction selected according to selection of a word line, adjacent cells are made different in the structure of cell capacitors. Such structural difference is realized by presence or absence of an impurity layer which has the same electrically-conductive type as a semiconductor substrate and higher in impurity concentration than the substrate between their storage nodes and the substrate, or by the difference in the surface area of the storage nodes when viewed from the substrate side, whereby when the semiconductor memory device is subjected to a single .alpha. ray at most one of the memory cells at least along the column direction causes a soft error.

摘要翻译： 半导体存储器件包括多个1比特存储单元，每个存储单元具有MOS晶体管和MOS电容器并且二维布置。 在根据字线的选择选择的沿着列方向的存储单元中，在单元电容器的结构中使相邻单元不同。 这种结构差异是通过存在或不存在具有与半导体衬底相同的导电类型和杂质浓度高于其存储节点和衬底之间的衬底的杂质层的存在或不存在，或通过其表面积的差异 当从基板侧观察存储节点时，至少在沿着列方向的半导体存储器件中存在至少一个存储单元的单个α射线时，导致软错误。